I just made a test bench log of T80 (log of instruction's M1, and first M1 coming after knowing that I send a lot of NOP after my instruction), and compare it to a JavaCPC timing array. Some instructions was not tested (interrupt wait, and special timing (instructions with change timing)), but all others passed correctly.
In r008.5.14, in GA, I do use begin of edge for IO_ACK instead of state.
In r008.5.14, M1 reached same time of IO_ACK are ignored (not M1) in WAIT_n generator.
In r008.5.14, MEM_WR has an OSD menu choice to switch between "quick" and "slow", "slow" mode does insert ONE WAIT_n during detection of MEM_WR. This switch exists because somes games are running in "slow" mode and others in "quick" mode. In fact it exists several instruction making MEM_wr, and adding each one ONE WAIT_n does result in different case of synchronization.
=== Test of a real Zilog 80 ===