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== Effort done ==Instruction timing : I tested instruction timing of T80 compare to instruction timing of JavaCPC emulator, I deduce also the memory access that had to be slow down Test of a real Zilog, in fact T80 of opencore run on rising_edge, and zilog run during low state, so for testing I had to indirectly do a downclock, it run, perhaps if I put buffer on zilog access I could clock it at normal speed, but as it run...
Alignment of HSYNC '''Instruction timing''' : a button I tested instruction timing of starter kit display HSYNC loopback lines, it's usefull to T80 compare to a Maxam test instruction timing of JavaCPC emulator, I deduce also the memory access that alternate color on themhad to be slow down
'''Test of a real Zilog 80''', in fact T80 of opencore run on rising_edge, and zilog run during low state, so for testing I had to indirectly do a downclock, it run, perhaps if I put buffer on zilog access I could clock it at normal speed, but as it run... '''Alignment of HSYNC Interrupt''' : a button of starter kit display HSYNC loopback lines, it's usefull to compare to a Maxam test that alternate color on them '''Sniffing of a real Amstrad''', I listen on some wires of my Amstrad CPC 6128 plus, but I can't access to VSYNC/HSYNC output of CRTC, so I have to buy another model to do this test. In fact you can listen at clock of Amstrad and overclock it after using FPGA DCM component, resulting a clock sequence insertion that permit to insert 4 operations during one tic of real Amstrad, that's it with FPGA DCM you can overclock output Amstrad clock signal for insert more operation, I use this tips for listening signals and saving it in stater kit asynchronous RAM (write, stop write, write, stop write... i'm a perfectionist paranoid...)
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