* See the document "Extra CPC Plus Hardware Information" for more details.
=== Horizontal and Vertical Sync (R3) ===
UM6845:
Bits 3..0 define Horizontal Sync Width. If 0 is programmed this gives a HSYNC width of 16.
=== Interlace and Skew (R8) ===
UM6845:
[[File:CRTC Interlace modes.png]]
=== UM6845R and R31 ===
R31 is described in the UM6845R documentation as "Dummy Register".
R31 doesn't exist on types 0,2,3,4.
=== UM6845R and R12/R13 ===
The UM6845R differs to other CRTC in respect of R12/R13.
In demos to make a display compatible with all CRTCs program R12/R13 when VCC!=0. This will then take effect at the next frame start.
=== UM6845R status register ===
The UM6845R has a status register that can be read using port &BExx.
All the other bits read as 0 and don't have any function.
=== ASIC/Pre-ASIC and R10/R11 ===
The cursor raster registers R10/R11 act as status registers on Types 3 & 4.