Real Amstrad use buffer memory in front of each address and data access, and real z80 is clock low state active. Normally if you follow datasheet of z80 you know how to map memory following CU comportment. Or you do as Amstrad, saying that z80 CU sucks, I create my own sequencer, managing all my memories access, alternating CRTC work and z80 work with little synchronization, insert by the way more pixels that can support my small CRTC...
=== Why NEXYS2 500kgates starter kit ===The first response is that is the one I have xP==== Xilinx schematics ====Xilinx webpack permit drawing schematics as book schematics, My point of view is : "For programming a FPGA, you draw a schematics as old book and just press one button. Each component on this schematic can be edit, in a language called VHDL". My source code is not Altera compatible because of schematics drawn, but webpack can export vhdl code from schematics if you want. ==== RAM dump ====
A starter kit that contain a RAM component can dump it.
My own made program do it with poor serial port, so for dumping all RAM content it take about 3 hours, and for dumping Amstrad RAM part it is about 15 minutes.
==== FPGA internal RAM size ====
It's to know that a FPGA chip contain 96KB internal RAM so you can't insert a dsk inside. This internal RAM is already used in part be T80 (z80 from opencores), the soundchip, and RAM asynchronous (RAM with two different speed one for writing another for reading) that I use for VGA mode.
==== VHDL components size ====
T80 (z80 processor) take 100kgates