Changes

The standard expansions are based on the RAM banking logic from the CPC6128, ie. equivalent This is handled by a PAL16L8 but to the programmer it appears to be the fourth register in the [[Gate Array]] register in . The I/O decoding is different to the CPC6128 (or more preciselyGate-Array.* PAL16L8 decodes A15=0 only* Gate-Array decodes A15=0 and A14=1 To access the RAM and Gate-Array port 7fxx is used. In addition the RAM answers when the data has bit 7=1 and bit 6=1, which is unused in the PAL that assists its Gate -Array chip).  External expansions have their own PAL or hardware which performs the same operation. Later CPC revisions with the costdown ASIC and the Plus have the RAM expansion logic inside their ASICs.

Expansions bigger than 64K combine the CPC6128-style mapping with some formerly unused chips bits in the fourth Gate Array registervalue written to the RAM select:

Gate Array, Port 7Fxxh: 7-6 Must be both set to 1 (aka Gate Array Register 3)

2 Special feature bit. For this kind of RAM banking it must be set to 1. "0" Enables special features. 1-0 Bank mapping in 16K fragments (RAM configuration as on normal CPC 6128 Gate Array)The 16K fragments are consisting of 8 banks. Banks 0-3 are the internal RAM, banks 4-7 are external RAM (CPC6128 taken from the currently selected 64K block).bank

s = Special function bit (1 = normal function) (D2 bit) cc cccc = mapping of 16K fragments configuration (as in CPC6128) (D0,D1 bits)

(*) For example 7B01h or 7B7Fh would be no good, because the FDC commandregister at FB7Fh is mirrored to these locations. Using 7B80h..7BFFh wouldfix that problem, but might conflict with other connected expansionhardware.