My source code is not Altera compatible because of schematics drawn, but webpack can export vhdl code from schematics if you want.
==== RAM dump ====A starter kit that contains a RAM component can dump it.
While power is on you A starter kit that contains a RAM component can :dump it.
-programming FPGA with a program/schematics done for filling RAMWhile power is on you can :
-*programming FPGA with a program/schematics done for filling RAM *press reset button -*programming FPGA with a program/schematics done for using RAM -*press reset button -*programming FPGA with a program/schematics done for reading RAM -*press reset button
My own made program do it with poor serial port, so for dumping all RAM content it takes about 3 hours, and for dumping Amstrad RAM part it is about 15 minutes.
