Changes
RAM contain lines of 0xFF, each finishing by 0x00, but lines are not in great order
==== Third schematic Z80+ROM+RAM+VGA ====
Goal is : RAM empty at startup, VGA displays hello after run.
So you put the two last schematic together and tadam... got a problem.
The problem is that two component are accessing RAM in the same time : the Z80 and the VGA, so you had to make a sequencer. A sequencer is simply a counter fed by a clock : 00, 01, 10, 11. And you manage work task like this :
*00 RAM WRITE start from Z80*01 RAM WRITE end from Z80 *10 RAM READ start from VGA *11 RAM READ end from VGA
To solve this problem you can use a special RAM done for this problem, a RAM that you can WRITE at a certain speed, and READ at another speed, this magic component is called '''ramb16_s16_s16'''. Note that they have no problem to write simultaneously on two RAM components, so that you can dump video RAM content using starter kit RAM, and you can display VGA using FPGA internal ramb16_s16_s16 RAM.
