Changes
/* Clock sequence */
Original Gatearray of Amstrad is a sequencer, it manage synchronization between video card and z80 and memory access.
Historically they are a link between CU of CU/ALU, and... control bus and... making a own sequencer. My theory is that clock can be absorbed by control bus, so that architecture can be seen as one common bus just called system-bus (= control-bus + data-bus + address-bus)But I will say more in order to not disturb these text part xD
Whatever, I made my own sequencer here in form of a bus of 4 wires called CLK4. CLK4 execute a simple repetitive sequence like 0001 0010 0011... CLK4(3), the last wire is directly connected to Z80 clock entry. Component not using explicit CLK4 as clock entry are generally using a not(CLK4(3)) entry, in order to do operation not as same time than z80.
Real Amstrad use buffer memory in front of each address and data access, and real z80 is clock low state active. Normally if you follow datasheet of z80 you know how to map memory following CU comportment. Or you do as Amstrad, saying that z80 CU sucks, I create my own sequencer, managing all my memories access, alternating CRTC work and z80 work with little synchronization, insert by the way more pixels that can support my small CRTC...
