Changes
'''You have to :'''
- program FPGA with the binary of this project, for it I use Digilent Adept software and my USB JTAG cable
'''You can :'''
- plug a PS/2 keyboard, and type "cat"
- plug a jack on slot JD1, one at upper GND plug, and second wire at next plug, just at left of it (if it was 3.3v Vcc, is that in fact you had to take the right one)
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== Tests done ==
'''Several bug could disappear in TV mode... but TV mode is not implemented yet.'''
prince.dsk gryzor.dsk donkey.dsk : critical bug : always writing on memory, certainly performance, have to test it on TV mode to know if it came from my asynchronous RAM.
buggyboy.dsk barbarian.dsk : raster bug can be fight with anti-raster switch (last switch is anti-raster, stopping ink rotate...)
longshot : VSYNC alternate cut bug, it's so warrior dam
crazycar2.dsk : simple overscan, my vga buffer is full lol
a lot of demos don't pass, in fact I didn't find one that pass dam.
'''Other bug is about dsk format :'''
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== Effort done ==
Instruction timing : I tested instruction timing of T80 compare to instruction timing of JavaCPC emulator, I deduce also the memory access that had to be slow down
Test of a real Zilog, in fact T80 of opencore run on rising_edge, and zilog run during low state, so for testing I had to indirectly do a downclock, it run, perhaps if I put buffer on zilog access I could clock it at normal speed, but as it run...
Alignment of HSYNC : a button of starter kit display HSYNC loopback lines, it's usefull to compare to a Maxam test that alternate color on them
Sniffing of real Amstrad, I listen on some wires of my Amstrad CPC 6128 plus, but I can't access to VSYNC/HSYNC output of CRTC, so I have to buy another model to do this test.
