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SP0256 Instruction Set

39 bytes added, 01:48, 5 January 2010
== Memory==
The SP0256 can address 60Kbytes (480Kbits) of internal or external ROM, however, usally the ROMs are only 2Kbytes (16Kbit). The ROM contains plain program code, without any kind of data arrays.
The upper 4bit of the program counter cannot be zero, so the memory starts at byte-address 1000h, and ends at FFFFh. The first 512 bytes are entrypoints, usually containing JUMP opcodes for up to 256 allophones or words.
The JUMP/CALL/RET opcodes can address only byte-aligned addresses, however, opcodes aren't always multiples of 8bits in size, so following opcodes may begin on any bit boundary.
== Opcode Summary==
0000b SETPAGE/RET Set Page for JUMP/CALL, or Return from CALL
0110b SETMSB_23 Load Amplitude, MSBs of 2 or 3 Coeffcients
0111b LOAD_PA Load Pitch, Amplitude
 
1000b LOAD_ALL Load All Parameters (at full 8bit precision)
1001b DELTA_56 Add Delta to Amplitude, Pitch, 5 or 6 Coefficients
1101b CALL Jump to Subroutine (12-bit PAGE-Relative Address)
1110b JUMP Jump to 12-bit PAGE-Relative Address
1111b PAUSE Silent Pause
1111b PAUSE Silent Pause== Opcodes ==
Opcode 1110b - JUMP - Jump to 12-bit PAGE-Relative Address
8 Coeff B4 signed ;\coeff pair 4
8 Coeff F4 signed ;/
 
8 Coeff B5 signed ;\coeff pair 5
8 Coeff F5 signed ;/
3/6 Coeff B2 Bit4/1..6 unsigned ;\coeff pair 2 ;
5/6 Coeff F2 Bit3/2..7 signed ;/ ;/
 
4/6 Coeff B3 Bit3/1..6 unsigned ;\coeff pair 3
6/7 Coeff F3 Bit2/1..7 signed ;/
6/7 New F3 MSBs signed ;\
6/8 New F4 MSBs signed ; Opcode SETMSB_23 only
 
(8) New F5 MSBs signed (when EXTRA=1 only) ;/
(0) Set F5=0 and B5=0 (when EXTRA=0 only)
The update to the amplitude register is a normal 2s complement update to the entire register. This means that any carry/borrow from the mantissa will change the value of the exponent. The update doesn't know anything about the format of that register.
== Credits==
The SP0256 opcodes were reverse engineered by Joe Zbiciak and Frank Palazzolo.
== Repeat Count = 0==
According to Joe and Frank, a repeat count of zero "causes the instruction to not execute" (and not to fetch any of its following paramters, so the opcode becomes only 8bits long; or to fetch, but not apply them?), however, they've also mentioned that "conflicting documentation suggests there's more going on".
== XXX...==
Bit fields narrower than 8 bits are MSB justified unless specified otherwise, meaning that the least significant bits are the ones that are missing. These LSBs are filled with zeros.
When updating filter coefficients with a delta-update, the microsequencer performs plain 2s-complement arithmetic on the 8-bit value in the coefficient register file. No attention is paid to the format of the register.
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