Changes
/* Technical */
== Technical ==
* The eagle schematics indicate INT is triggered, but the layouts indicate NMI is connected.
* the static RAM is accessible between 0-1fff. It could be mirrored between 2000-3fff.
* Has a write only I/O port where A10=0 and A2=0. A8 of the port address (when '1'?) is used to 'activate' the ROMDIS signal (see IC1A) causing the CPC's ROM to be disabled. The static ram is then readable in the address space from 0-fff. A9 of the port address (when '1'?) (see IC1B) is used to 'activate' the RAMDIS signal causing the CPC's RAM to be disabled. This allows the static RAM to be read/written in the range 1000-1fff since access depends on A12 (see IC7A). It's not clear if both are visible.
