[[image:Z80A.jpg|thumb|Zilog Z80A]]
Microprocessor from Zilog, wich which is used in the Amstrad CPC Computers. The Z80/Z80A was a very popular microprocessor, used in a great variety of home computers and appliances as far-fetched as satelitessatellites. It was even used in the Commodore C128 as a secondary processor in order to achieve [[CP/M]] compatibility. == Description == The Z80 microprocessor is an 8 bit [[CPU]] with a 16 bit address bus capable of direct access to 64k of memory space. It has a language of 252 root instructions and with the reserved 4 bytes as prefixes, access to an additional 308 instructions. The Z80 was modelled after the [[8080]] and contains the seventy-eight 8080 opcodes as a subset to its language. Programming features include an accumulator and six 8-bit registers that can be paired as three 16-bit registers. In addition to the general registers, a stack pointer, program counter, and two index (memory pointer) registers are provided. While not in the same league as the Intel 80x86 or the [[Motorola 68000]] series, the Z80 is extremely useful for low cost control applications. One of the more useful features of the Z80 is the built-in refresh circuitry for ease of design with DRAMs. The Z80 comes in a 40 pin DIP package. It has been manufactured in A, B, and C models, differing only in maximum clock speed. It also has been manufactured as a stand-alone microcontroller with various configurations of on-chip RAM and EPROM. == Part numbers used in the Amstrad CPC during its lifetime == The Z80 CPU has been manufactured by others, and various Z80s have been used in the construction of the CPC during its lifetime. * SGS Z8400AB1* ST Z8400AB1* ZILOG Z8400APS* ZILOG Z0840004PSC === modern incarnatinons ==={{stub}} Apart from surplus/new Z80-clones that are quite easy to find, many emulations depend on software implementations of the Z80: * The [[T80]] is a [[VHDL|VHDL]] implementation of the Z80 and Z80A, finished in 2002 on [[OpenCores|OpenCores]]* [[arnold]] uses [[InkZ80]], written in C++ (apart from the author-designed C simulation)* On OpenCores, there is also a [[Verilog|Verilog]] implementation of the Z80. [[Zilog]] itself offers the [[eZ80|eZ80]] processor, a new, 50MHz design. Kits now have reached a less-than-prohibitive price range and may be available without a business.
== See also ==
* [[Z80 - undocumented opcodes]]
* [[Media:Z80 CPC Timings cheat sheet.20230709.pdf]]
== Tutorials Block Diagram ==[[File:Z80 Block Diagram.gif]]
== Manuals ==
*[[Media:Um0080.pdf|Official Zilog Z80 CPU user manual (2016)]]
*[[Media:Z80 CPU Technical Manual 1977.pdf]]
*[[Media:Mostek Z80 Programming Manual.pdf]]
== Weblinks ==
*[[Zilog]] [http://www.zilog.com]
*[http://www.z80.info/z80cs.htm Computer Systems based on Z80 Family]
*[http://en.wikipedia.org/wiki/Z80 The Z80 processor on Wikipedia]
*[https://www.grimware.org/doku.php/documentations/devices/z80 Z80 documentation from Grimware]
== Opcodes ==
Check the end of the document for explanations of abbreviations used below.
=== Alfabethical list ===
{|{{Prettytable|width: 700px; font-size: 2em;}}
|''Mnemonic''||''Clock''||''Size''||''SZHPNC''||''Opcode''||''Description||''Notes''
|- style="background:#efefef;"
|ADC A, r||4||1||rowspan=5|*** V0 *||88 + rb||rowspan=5|Add with Carry||rowspan=5|A = A + s + CY
|- style="background:#efefef;"
|ADC A, N||7||2||||CE XX
|- style="background:#efefef;"
|ADC A, (HL)||7||1||||8E
|- style="background:#efefef;"
|ADC A, (IX + N)||19||3||||DD 8E XX
|- style="background:#efefef;"
|ADC A, (IY + N)||19||3||||FD 8E XX
|-
|ADC HL, BC||15||2||rowspan=4|**? V0 *||ED 4A||rowspan=4|Add with Carry||rowspan=4|HL = HL + ss + CY
|-
|ADC HL, DE||15||2||||ED 5A
|-
|ADC HL, HL||15||2||||ED 6A
|-
|ADC HL, SP||15||2||||ED 7A
|- style="background:#efefef;"
|ADD A, r||4||1||rowspan=5|*** V0 *||80 + rb||rowspan=5|Add (8-bit)||rowspan=5|A = A + s
|- style="background:#efefef;"
|ADD A, N||7||2||||C6 XX
|- style="background:#efefef;"
|ADD A, (HL)||7||1||||86
|- style="background:#efefef;"
|ADD A, (IX + N)||19||3||||DD 86 XX
|- style="background:#efefef;"
|ADD A, (IY + N)||19||3||||FD 86 XX
|-
|ADD HL, BC||11||1||rowspan=4|--?- 0 *||09||rowspan=4|Add (16-bit)||rowspan=4|HL = HL + ss
|-
|ADD HL, DE||11||1||||19
|-
|ADD HL, HL||11||1||||29
|-
|ADD HL, SP||11||1||||39
|- style="background:#efefef;"
|ADD IX, BC||15||2||rowspan=4|--?- 0 *||DD 09||rowspan=4|Add (IX register)||rowspan=4|IX = IX + pp
|- style="background:#efefef;"
|ADD IX, DE||15||2|||| DD 19
|- style="background:#efefef;"
|ADD IX, IX||15||2|||| DD 29
|- style="background:#efefef;"
|ADD IX, SP||15||2|||| DD 39
|-
|ADD IY, BC||15||2||rowspan=4|--?- 0 *||FD 09||rowspan=4|Add (IY register)||rowspan=4|IY = IY + rr
|-
|ADD IY, ||15||2||||FD 19
|-
|ADD IY, IY||15||2||||FD 29
|-
|ADD IY, SP||15||2||||FD 39
|- style="background:#efefef;"
|AND r||4||1||rowspan=5|***P00||A0+rb||rowspan=5|Logical AND||rowspan=5|A=A&s
|- style="background:#efefef;"
|AND N||7||2||||E6 XX
|- style="background:#efefef;"
|AND (HL)||7||1||||A6
|- style="background:#efefef;"
|AND (IX+N)||19||3||||DD A6 XX
|- style="background:#efefef;"
|AND (IY+N)||19||3||||FD A6 XX
|-
|BIT b,r||8||2||rowspan=4|?*1?0-||CB 40+8*b+rb||rowspan=4|Test Bit||rowspan=4|m&{2^b}||
|-
|BIT b,(HL)||12||2||||CB 46+8*b
|-
|BIT b,(IX+N)||20||4||||DD CB XX 46+8*b
|-
|BIT b,(IY+N)||20||4||||FD CB XX 46+8*b
|- style="background:#efefef;"
|CALL NN||17||3||------||CD XX XX||Unconditional Call||-(SP)=PC,PC=nn
|-
|CALL C,NN||17/1||3||rowspan=8|------||DC XX XX||rowspan=8|Conditional Call||If Carry = 1
|-
|CALL NC,NN||17/1||3||||D4 XX XX||If carry = 0
|-
|CALL M,NN||17/1||3||||FC XX XX||If Sign = 1 (negative)
|-
|CALL P,NN||17/1||3||||F4 XX XX||If Sign = 0 (positive)
|-
|CALL Z,NN||17/1||3||||CC XX XX||If Zero = 1 (ans.=0)
|-
|CALL NZ,NN||17/1||3||||C4 XX XX||If Zero = 0 (non-zero)
|-
|CALL PE,NN||17/1||3||||EC XX XX||If Parity = 1 (even)
|-
|CALL PO,NN||17/1||3||||E4 XX XX||If Parity = 0 (odd)
|- style="background:#efefef;"
|CCF||4||1||--?-0*||3F||Complement Carry Flag||CY=~CY
|-
|CP r||4||1||rowspan=5|***V1*||B8+rb||rowspan=5|Compare||rowspan=5|Compare A-s
|-
|CP N||7||2||||FE XX
|-
|CP (HL)||7||1||||BE
|-
|CP (IX+N)||19||3||||DD BE XX
|-
|CP (IY+N)||19||3||||FD BE XX
|-
|CPD||16||2||****1-||ED A9||Compare and Decrement||A-(HL),HL=HL-1,BC=BC-1
|DAA||4||1||***P-*||27||Decimal Adjust Acc.||A=BCD format (dec.)
|- style="background:#efefef;"
|DEC A||4||1||rowspan=10|***V1-||3D||rowspan=10|Decrement (8-bit)||rowspan=10|s=s-1|- style="background:#efefef;"|DEC B||4||1||||05|- style="background:#efefef;"|DEC C||4||1||||0D|- style="background:#efefef;"|DEC D||4||1||||15|- style="background:#efefef;"|DEC E||4||1||||1D|- style="background:#efefef;"|DEC H||4||1||||25|- style="background:#efefef;"|DEC L||4||2||||2D|- style="background:#efefef;"|DEC (HL)||11||1||||35|- style="background:#efefef;"|DEC (IX+N)||23||3||||DD 35 XX|- style="background:#efefef;"|DEC (IY+N)||23||3||||FD 35 XX
|-
|DEC BC||6||1||rowspan=4|------||0B||rowspan=4|Decrement (16-bit)||rowspan=4|ss=ss-1
|-
|DEC DE||6||1||||1B
|-
|DEC HL||6||1||||2B
|-
|DEC SP||6||1||||3B
|- style="background:#efefef;"
|DEC IX||10||2||rowspan=2|------||DD 2B||rowspan=2|Decrement||rowspan=2|xx=xx-1
|- style="background:#efefef;"
|DEC IY||10||2||||FD 2B
|-
|DI||4||1||------||F3||Disable Interrupts||
|EI||4||1||------||FB||Enable Interrupts||
|- style="background:#efefef;"
|EX (SP),HL||19||1||rowspan=5|------||E3||rowspan=5|Exchange||(SP)<->HL
|- style="background:#efefef;"
|EX (SP),IX||23||2||------||DD E3||(SP)<->xx
|- style="background:#efefef;"
|EX (SP),IY||23||2|| ||FD E3||
|- style="background:#efefef;"
|EX AF,AF'||4||1||------||08||AF<->AF'
|- style="background:#efefef;"
|EX DE,HL||4||1||------||EB||DE<->HL
|- style="background:#efefef;"
|EXX||4||1||------||D9||Exchange||qq<->qq' (except AF)
|HALT||4||1||------||76||Halt||
|- style="background:#efefef;"
|IM 0||8||2||rowspan=3|------||ED 46||rowspan=3|Interrupt Mode ||rowspan=3|(n=0,1,2)|
|- style="background:#efefef;"
|IM 1||8||2||||ED 56
|- style="background:#efefef;"
|IM 2||8||2||||ED 5E
|-
|IN A,(N)||11||2||------||DB XX||Input||A=(n)
|IN (C)||12||2||***P0-||ED 70||Input*||(Unsupported)
|-
|IN A,(C)||12||2||rowspan=7|***P0-||ED 78||rowspan=7|Input||rowspan=7|r=(C)
|-
|IN B,(C)||12||2||||ED 40
|-
|IN C,(C)||12||2||||ED 48
|-
|IN D,(C)||12||2||||ED 50
|-
|IN E,(C)||12||2||||ED 58
|-
|IN H,(C)||12||2||||ED 60
|-
|IN L,(C)||12||2||||ED 68
|- style="background:#efefef;"
|INC A||4||1||rowspan=7|***V0-||3C||rowspan=7|Increment (8-bit)||rowspan=7|r=r+1
|- style="background:#efefef;"
|INC B||4||1||||04
|- style="background:#efefef;"
|INC C||4||1||||0C
|- style="background:#efefef;"
|INC D||4||1||||14
|- style="background:#efefef;"
|INC E||4||1||||1C
|- style="background:#efefef;"
|INC H||4||1||||24
|- style="background:#efefef;"
|INC L||4||1||||2C
|-
|INC BC||6||1||rowspan=4|------||03||rowspan=4|Increment (16-bit)||rowspan=4|ss=ss+1
|-
|INC DE||6||1||||13
|-
|INC HL||6||1||||23
|-
|INC SP||6||1||||33
|- style="background:#efefef;"
|INC IX||10||2||rowspan=2|------||DD 23||rowspan=2|Increment||rowspan=2|xx=xx+1
|- style="background:#efefef;"
|INC IY||10||2||||FD 23
|-
|INC (HL)||11||1||***V0-||34||Increment (indirect)||(HL)=(HL)+1
|- style="background:#efefef;"
|INC (IX+N)||23||3||rowspan=2|***V0-||DD 34 XX||rowspan=2|Increment||rowspan=2|(xx+d)=(xx+d)+1
|- style="background:#efefef;"
|INC (IY+N)||23||3||||FD 34 XX
|-
|IND||16||2||?*??1-||ED AA||Input and Decrement||(HL)=(C),HL=HL-1,B=B-1
|INIR||21/1||2||?1??1-||ED B2||Input, Inc., Repeat||INI till B=0
|- style="background:#efefef;"
|JP NN||10||3||rowspan=4|------||C3 XX XX||rowspan=4|Unconditional Jump||PC=nn
|- style="background:#efefef;"
|JP (HL)||4||1||------||E9||PC=(HL)
|- style="background:#efefef;"
|JP (IX)||8||2||------||DD E9||rowspan=2|PC=(xx)
|- style="background:#efefef;"
|JP (IY)||8||2||||FD E9
|-
|JP C,$NN||10/1||3||rowspan=8|------||DA XX XX||rowspan=8|Conditional Jump||If Carry = 1
|-
|JP NC,$NN||10/1||3||||D2 XX XX||If Carry = 0
|-
|JP M,$NN||10/1||3||||FA XX XX||If Sign = 1 (negative)
|-
|JP P,$NN||10/1||3||||F2 XX XX||If Sign = 0 (positive)
|-
|JP Z,$NN||10/1||3||||CA XX XX||If Zero = 1 (ans.= 0)
|-
|JP NZ,$NN||10/1||3||||C2 XX XX||If Zero = 0 (non-zero)
|-
|JP PE,$NN||10/1||3||||EA XX XX||If Parity = 1 (even)
|-
|JP PO,$NN||10/1||3||||E2 XX XX||If Parity = 0 (odd)
|- style="background:#efefef;"
|JR $N+2||12||2||------||18 XX||Relative Jump||PC=PC+e
|-
|JR C,$N+2||12/7||2||rowspan=4|------||38 XX||rowspan=4|Cond. Relative Jump||rowspan=4|If cc JR(cc=C,NC,NZ,Z)
|-
|JR NC,$N+2||12/7||2||||30 XX
|-
|JR Z,$N+2||12/7||2||||28 XX
|-
|JR NZ,$N+2||12/7||2||||20 XX
|- style="background:#efefef;"
|LD I,A||9||2||rowspan=2|------||ED 47||rowspan=2|Load*||rowspan=2|dst=src
|- style="background:#efefef;"
|LD R,A||9||2||||ED 4F
|-
|LD A,I||9||2||rowspan=2|**0*0-||ED 57||rowspan=2|Load*||rowspan=2|dst=src
|-
|LD A,R||9||2||||ED 5F
|- style="background:#efefef;"
|LD A,r||4||1||rowspan=38|------||78+rb||rowspan=38|Load (8-bit)||rowspan=38|dst=src
|- style="background:#efefef;"
|LD A,N||7||2||||3E XX
|- style="background:#efefef;"
|LD A,(BC)||7||1||||0A
|- style="background:#efefef;"
|LD A,(DE)||7||1||||1A
|- style="background:#efefef;"
|LD A,(HL)||7||1||||7E
|- style="background:#efefef;"
|LD A,(IX+N)||19||3||||DD 7E XX
|- style="background:#efefef;"
|LD A,(IY+N)||19||3||||FD 7E XX
|- style="background:#efefef;"
|LD A,(NN)||13||3||||3A XX XX
|- style="background:#efefef;"
|LD B,r||4||1||||40+rb
|- style="background:#efefef;"
|LD B,N||7||2||||06 XX
|- style="background:#efefef;"
|LD B,(HL)||7||1||||46
|- style="background:#efefef;"
|LD B,(IX+N)||19||3||||DD 46 XX
|- style="background:#efefef;"
|LD B,(IY+N)||19||3||||FD 46 XX
|- style="background:#efefef;"
|LD C,r||4||1||||48+rb
|- style="background:#efefef;"
|LD C,N||7||2||||0E XX
|- style="background:#efefef;"
|LD C,(HL)||7||1||||4E
|- style="background:#efefef;"
|LD C,(IX+N)||19||3||||DD 4E XX
|- style="background:#efefef;"
|LD C,(IY+N)||19||3||||FD 4E XX
|- style="background:#efefef;"
|LD D,r||4||1||||50+rb
|- style="background:#efefef;"
|LD D,N||7||2||||16 XX
|- style="background:#efefef;"
|LD D,(HL)||7||1||||56
|- style="background:#efefef;"
|LD D,(IX+N)||19||3||||DD 56 XX
|- style="background:#efefef;"
|LD D,(IY+N)||19||3||||FD 56 XX
|- style="background:#efefef;"
|LD E,r||4||1||||58+rb
|- style="background:#efefef;"
|LD E,N||7||2||||1E XX
|- style="background:#efefef;"
|LD E,(HL)||7||1||||5E
|- style="background:#efefef;"
|LD E,(IX+N)||19||3||||DD 5E XX
|- style="background:#efefef;"
|LD E,(IY+N)||19||3||||FD 5E XX
|- style="background:#efefef;"
|LD H,r||4||1||||60+rb
|- style="background:#efefef;"
|LD H,N||7||2||||26 XX
|- style="background:#efefef;"
|LD H,(HL)||7||1||||66
|- style="background:#efefef;"
|LD H,(IX+N)||19||3||||DD 66 XX
|- style="background:#efefef;"
|LD H,(IY+N)||19||3||||FD 66 XX
|- style="background:#efefef;"
|LD L,r||4||1||||68+rb
|- style="background:#efefef;"
|LD L,N||7||2||||2E XX
|- style="background:#efefef;"
|LD L,(HL)||7||1||||6E
|- style="background:#efefef;"
|LD L,(IX+N)||19||3||||DD 6E XX
|- style="background:#efefef;"
|LD L,(IY+N)||19||3||||FD 6E XX
|-
|LD BC,(NN)||20||4||rowspan=15|------||ED 4B XX XX ||rowspan=15|Load (16-bit)||rowspan=15|dst=src
|-
|LD BC,NN||10||3||||01 XX XX
|-
|LD DE,(NN)||20||4||||ED 5B XX XX
|-
|LD DE,NN||10||3||||11 XX XX
|-
|LD HL,(NN)||20||3||||2A XX XX
|-
|LD HL,NN||10||3||||21 XX XX
|-
|LD SP,(NN)||20||4||||ED 7B XX XX
|-
|LD SP,HL||6||1||||F9
|-
|LD SP,IX||10||2||||DD F9
|-
|LD SP,IY||10||2||||FD F9
|-
|LD SP,NN||10||3||||31 XX XX
|-
|LD IX,(NN)||20||4||||DD 2A XX XX
|-
|LD IX,NN||14||4||||DD 21 XX XX
|-
|LD IY,(NN)||20||4||||FD 2A XX XX
|-
|LD IY,NN||14||4||||FD 21 XX XX
|-
|LD (HL),r||7||1||rowspan=15|------||70+rb||rowspan=15|Load (Indirect)||rowspan=15|dst=src
|-
|LD (HL),N||10||2||||36 XX
|-
|LD (BC),A||7||1||||02
|-
|LD (DE),A||7||1||||12
|-
|LD (NN),A||13||3||||32 XX XX
|-
|LD (NN),BC||20||4||||ED 43 XX XX
|-
|LD (NN),DE||20||4||||ED 53 XX XX
|-
|LD (NN),HL||16||3||||22 XX XX
|-
|LD (NN),IX||20||4||||DD 22 XX XX
|-
|LD (NN),IY||20||4||||FD 22 XX XX
|-
|LD (NN),SP||20||4||||ED 73 XX XX
|-
|LD (IX+N),r||19||3||||DD 70+rb XX
|-
|LD (IX+N),N||19||4||||DD 36 XX XX
|-
|LD (IY+N),r||19||3||||FD 70+rb XX
|-
|LD (IY+N),N||19||4||||FD 36 XX XX
|-
|LDD||16||2||--0*0-||ED A8||Load and Decrement||(DE)=(HL),HL=HL-1,#
|NEG||8||2||***V1*||ED 44||Negate||A=-A
|-
|NOP||4||1||------||00||No Operation||||
|-
|OR r||4||1||rowspan=5|***P00||B0+rb||rowspan=5|Logical inclusive OR||rowspan=5|A=Avs
|-
|OR N||7||2||||F6 XX
|-
|OR (HL)||7||1||||B6
|-
|OR (IX+N)||19||3||||DD B6 XX
|-
|OR (IY+N)||19||3||||FD B6 XX
|-
|OUT (N),A||11||2||rowspan=9|------||D3 XX||Output||(n)=A
|-
|OUT (C),0||12||2||------||ED 71||Output*||(Unsupported)
|-
|OUT (C),A||12||2||------||ED 79||rowspan=7|Output||rowspan=7|(C)=r
|-
|OUT (C),B||12||2||||ED 41
|-
|OUT (C),C||12||2||||ED 49
|-
|OUT (C),D||12||2||||ED 51
|-
|OUT (C),E||12||2||||ED 59
|-
|OUT (C),H||12||2||||ED 61
|-
|OUT (C),L||12||2||||ED 69
|-
|OUTD||16||2||?*??1-||ED AB||Output and Decrement||(C)=(HL),HL=HL-1,B=B-1
|OTDR||21/1||2||?1??1-||ED BB||Output, Dec., Repeat||OUTD till B=0
|-
|OUTI||16||2||?*??1-||ED A3||Output and Increment||(C)=(HL),HL=HL+1,B=B-1
|-
|OTIR||21/1||2||?1??1-||ED B3||Output, Inc., Repeat||OUTI till B=0
|-
|POP AF||10||1||rowspan=4|------||F1||rowspan=4|Pop||rowspan=4|qq=(SP)+
|-
|POP BC||10||1||||C1
|-
|POP DE||10||1||||D1
|-
|POP HL||10||1||||E1
|-
|POP IX||14||2||rowspan=2|------||DD E1||rowspan=2|Pop||rowspan=2|xx=(SP)+
|-
|POP IY||14||2||||FD E1|||||||} {|{{Prettytable|width: 700px; font-size: 2em;}}|''Mnemonic''||''Clock''||''Size''||''SZHPNC''||''Opcode''||''Description||''Notes''
|-
|PUSH AF||11||1||rowspan=4|------||F5||rowspan=4|Push||rowspan=4|(SP)=qq
|-
|PUSH BC||11||1||C5|
|-
|PUSH DE||11||1||D5|
|-
|PUSH HL||11||1||E5|
|-
|PUSH IX||15||2||rowspan=2|------||DD E5||rowspan=2|Push||rowspan=2|-(SP)=xx
|-
|PUSH IY||15||2||||FD E5|
|-
|RES b,r||8||2||rowspan=4|------||CB 80+8*b+rb||rowspan=4|Reset bit||rowspan=4|m=m&{~2^b}|
|-
|RES b,(HL)||15||2||------||CB 86+8*b|||
|-
|RES b,(IX+N)||23||4||------||DD CB XX 86+8*b|||
|-
|RES b,(IY+N)||23||4||FD CB XX 86+8*b|-|RET||10||1||rowspan=9|------||C9||Return||PC=(SP)+|-|RET C||11/5||1||D8||rowspan=8|Conditional Return||If Carry = 1|-|RET NC||11/5||1||D0||If Carry = 0|-|RET M||11/5||1||F8||If Sign = 1 (negative)|-|RET P||11/5||1||F0||If Sign = 0 (positive)|-|RET Z||11/5||1||C8||If Zero = 1 (ans.=0)|-|RET NZ||11/5||1||C0||If Zero = 0 (non-zero)|-|RET PE||11/5||1||E8||If Parity = 1 (even)|-|RET PO||11/5||1||E0||If Parity = 0 (odd)|-|RET||10||1||------||C9||Return||PC=(SP)+|-|RET C||11/5||1||rowspan=8|------||D8||rowspan=8|Conditional Return||If Carry = 1|-|RET NC||11/5||1||D0||If Carry = 0|-|RET M||11/5||1||F8||If Sign = 1 (negative)|-|RET P||11/5||1||F0||If Sign = 0 (positive)|-|RET Z||11/5||1||C8||If Zero = 1 (ans.=0)|-|RET NZ||11/5||1||C0||If Zero = 0 (non-zero)|-|RET PE||11/5||1||E8||If Parity = 1 (even)|-|RET PO||11/5||1||E0||If Parity = 0 (odd)|-|RETI||14||2||------||ED 4D||Return from Interrupt||PC=(SP)+|-|RETN||14||2||------||ED 45||Return from NMI||PC=(SP)+|-|RLA||4||1||--0-0*||17||Rotate Left Acc.||A={CY,A}<-|-|RL r||8||2||rowspan=4|**0P0*||CB 10+rb||rowspan=4|Rotate Left||rowspan=4|m={CY,m}<-|-|RL (HL)||15||2||CB 16|-|RL (IX+N)||23||4||DD CB XX 16|-|RL (IY+N)||23||4||FD CB XX 8616|-|RLCA||4||1||--0-0*||07||Rotate Left Cir. Acc.||A=A<-|-|RLC r||8||2||rowspan=4|**0P0*||CB 00+rb||rowspan=4|Rotate Left Circular||rowspan=4|m=m<-|-|RLC (HL)||15||2||CB 06|-|RLC (IX+N)||23||4||DD CB XX 06|-|RLC (IY+N)||23||4||FD CB XX 06|-|RLD||18||2||**0P0-||ED 6F||Rotate Left 4 bits||{A,(HL)}={A,(HL)}<- ##|-|RRA||4||1||--0-0*||1F||Rotate Right Acc.||A=->{CY,A}|-|RR r||8||2||rowspan=4|**0P0*||CB 18+rb||rowspan=4|Rotate Right||rowspan=4|m=->{CY,m}|-|RR (HL)||15||2||CB 1E|-|RR (IX+N)||23||4||DD CB XX 1E|-|RR (IY+N)||23||4||FD CB XX 1E|-|RRCA||4||1||--0-0*||0F||Rotate Right Cir.Acc.||A=->A|-|RRC r||8||2||rowspan=4|**0P0*||CB 08+rb||rowspan=4|Rotate Right Circular||rowspan=4|m=->m|-|RRC (HL)||15||2||CB 0E|-|RRC (IX+N)||23||4||DD CB XX 0E|-|RRC (IY+N)||23||4||FD CB XX 0E|-|RRD||18||2||**0P0-||ED 67||Rotate Right 4 bits||{A,(HL)}=->{A,(HL)} ##|-|RST 0||11||1||rowspan=8|------||C7||rowspan=8|Restart||rowspan=8|(p=0H,8H,10H,...,38H)|-|RST 08H||11||1||CF|-|RST 10H||11||1||D7|-|RST 18H||11||1||DF|-|RST 20H||11||1||E7|-|RST 28H||11||1||EF|-|RST 30H||11||1||F7|-|RST 38H||11||1||FF|-|SBC r||4||1||rowspan=5|***V1*||98+rb|| rowspan=5|Subtract with Carry|| rowspan=5|A=A-s-CY|-|SBC A,N||7||2||DE XX|-|SBC (HL)||7||1||9E|-|SBC A,(IX+N)||19||3||DD 9E XX|-|SBC A,(IY+N)||19||3||FD 9E XX|-|SBC HL,BC||15||2||rowspan=4|**?V1*||ED 42||rowspan=4|Subtract with Carry||rowspan=4|HL=HL-ss-CY|-|SBC HL,DE||15||2||ED 52|-|SBC HL,HL||15||2||ED 62|-|SBC HL,SP||15||2||ED 72|-|SCF||4||1||--0-01||37||Set Carry Flag||CY=1|-|SET b,r||8||2||rowspan=4|------||CB C0+8*b+rb||rowspan=4|Set bit||rowspan=4|m=mv{2^b}|-|SET b,(HL)||15||2||CB C6+8*b|-|SET b,(IX+N)||23||4||DD CB XX C6+8*b|-|SET b,(IY+N)||23||4||FD CB XX C6+8*b|-|SLA r||8||2||rowspan=4|**0P0*||CB 20+rb||rowspan=4|Shift Left Arithmetic||rowspan=4|m=m*2|-|SLA (HL)||15||2||CB 26|-|SLA (IX+N)||23||4||DD CB XX 26|-|SLA (IY+N)||23||4||FD CB XX 26|-|SRA r||8||2||rowspan=4|**0P0*||CB 28+rb||rowspan=4|Shift Right Arith.||rowspan=4|m=m/2|-|SRA (HL)||15||2||CB 2E|-|SRA (IX+N)||23||4||DD CB XX 2E|-|SRA (IY+N)||23||4||FD CB XX 2E|-|SLL r||8||2||rowspan=4|**0P0*||CB 30+rb||rowspan=4|Shift Left Logical*||rowspan=4|m={0,m,CY}<-(SLL Instructionsare unsupported)|-|SLL (HL)||15||2||CB 36|-|SLL (IX+N)||23||4||DD CB XX 36|-|SLL (IY+N)||23||4||FD CB XX 36|-|SRL r||8||2||rowspan=4|**0P0*||CB 38+rb||rowspan=4|Shift Right Logical||rowspan=4|m=->{0,m,CY}|-|SRL (HL)||15||2||CB 3E|-|SRL (IX+N)||23||4||DD CB XX 3E|-|SRL (IY+N)||23||4||FD CB XX 3E|-|SUB r||4||1||rowspan=5|***V1*||90+rb||rowspan=5|Subtract||rowspan=5|A=A-s|-|SUB N||7||2||D6 XX|-|SUB (HL)||7||1||96|-|SUB (IX+N)||19||3||DD 96 XX|-|SUB (IY+N)||19||3||FD 96 XX|-|XOR r||4||1||rowspan=5|***P00||A8+rb||rowspan=5|Logical Exclusive OR||rowspan=5|A=Axs|-|XOR N||7||2||EE XX|-|XOR (HL)||7||1||AE|-|XOR (IX+N)||19||3||DD AE XX|-|XOR (IY+N)||19||3||FD AE XX
|}
=== Sorted by opcode ===
=== Ordered by function ===
+-------------+----+---+------+------------+---------------------+----------------------+ +-------------+----+---+------+------------+---------------------+----------------------+|RET | 10 | 1 |------|C9 |Return |PC=(SP)+ ||RET C |11/5| 1 |------|D8 |Conditional Return |If Carry = 1 ||RET NC |11/5| 1 | |D0 | |If Carry = 0 ||RET M |11/5| 1 | |F8 | |If Sign = 1 (negative)||RET P |11/5| 1 | |F0 | |If Sign = 0 (positive)||RET Z |11/5| 1 | |C8 | |If Zero = 1 (ans.=0) ||RET NZ |11/5| 1 | |C0 | |If Zero = 0 (non-zero)||RET PE |11/5| 1 | |E8 | |If Parity = 1 (even) ||RET PO |11/5| 1 | |E0 | |If Parity = 0 (odd) |+-------------+----+---+------+------------+---------------------+----------------------+|RETI | 14 | 2 |------|ED 4D |Return from Interrupt|PC=(SP)+ ||RETN | 14 | 2 |------|ED 45 |Return from NMI |PC=(SP)+ |+-------------+----+---+------+------------+---------------------+----------------------+|RLA | 4 | 1 |--0-0*|17 |Rotate Left Acc. |A={CY,A}<- ||RL r | 8 | 2 |**0P0*|CB 10+rb |Rotate Left |m={CY,m}<- ||RL (HL) | 15 | 2 | |CB 16 | | ||RL (IX+N) | 23 | 4 | |DD CB XX 16 | | ||RL (IY+N) | 23 | 4 | |FD CB XX 16 | | ||RLCA | 4 | 1 |--0-0*|07 |Rotate Left Cir. Acc.|A=A<- ||RLC r | 8 | 2 |**0P0*|CB 00+rb |Rotate Left Circular |m=m<- ||RLC (HL) | 15 | 2 | |CB 06 | | ||RLC (IX+N) | 23 | 4 | |DD CB XX 06 | | ||RLC (IY+N) | 23 | 4 | |FD CB XX 06 | | ||RLD | 18 | 2 |**0P0-|ED 6F |Rotate Left 4 bits |{A,(HL)}={A,(HL)}<- ##||RRA | 4 | 1 |--0-0*|1F |Rotate Right Acc. |A=->{CY,A} ||RR r | 8 | 2 |**0P0*|CB 18+rb |Rotate Right |m=->{CY,m} ||RR (HL) | 15 | 2 | |CB 1E | | ||RR (IX+N) | 23 | 4 | |DD CB XX 1E | | ||RR (IY+N) | 23 | 4 | |FD CB XX 1E | | ||RRCA | 4 | 1 |--0-0*|0F |Rotate Right Cir.Acc.|A=->A ||RRC r | 8 | 2 |**0P0*|CB 08+rb |Rotate Right Circular|m=->m ||RRC (HL) | 15 | 2 | |CB 0E | | ||RRC (IX+N) | 23 | 4 | |DD CB XX 0E | | ||RRC (IY+N) | 23 | 4 | |FD CB XX 0E | | ||RRD | 18 | 2 |**0P0-|ED 67 |Rotate Right 4 bits |{A,(HL)}=->{A,(HL)} ##|+-------------+----+---+------+------------+---------------------+----------------------+|RST 0 | 11 | 1 |------|C7 |Restart | (p=0H,8H,10H,...,38H)||RST 08H | 11 | 1 | |CF | | ||RST 10H | 11 | 1 | |D7 | | ||RST 18H | 11 | 1 | |DF | | ||RST 20H | 11 | 1 | |E7 | | ||RST 28H | 11 | 1 | |EF | | ||RST 30H | 11 | 1 | |F7 | | ||RST 38H | 11 | 1 | |FF | | |+-------------+----+---+------+------------+---------------------+----------------------+|SBC r | 4 | 1 |***V1*|98+rb |Subtract with Carry |A=A-s-CY ||SBC A,N | 7 | 2 | |DE XX | | ||SBC (HL) | 7 | 1 | |9E | | ||SBC A,(IX+N) | 19 | 3 | |DD 9E XX | | ||SBC A,(IY+N) | 19 | 3 | |FD 9E XX | | ||SBC HL,BC | 15 | 2 |**?V1*|ED 42 |Subtract with Carry |HL=HL-ss-CY ||SBC HL,DE | 15 | 2 | |ED 52 | | ||SBC HL,HL | 15 | 2 | |ED 62 | | ||SBC HL,SP | 15 | 2 | |ED 72 | | |+-------------+----+---+------+------------+---------------------+----------------------+|SCF | 4 | 1 |--0-01|37 |Set Carry Flag |CY=1 |+-------------+----+---+------+------------+---------------------+----------------------+|SET b,r | 8 | 2 |------|CB C0+8*b+rb|Set bit |m=mv{2^b} ||SET b,(HL) | 15 | 2 | |CB C6+8*b | | ||SET b,(IX+N) | 23 | 4 | |DD CB XX C6+8*b | ||SET b,(IY+N) | 23 | 4 | |FD CB XX C6+8*b | |+-------------+----+---+------+------------+---------------------+----------------------+|SLA r | 8 | 2 |**0P0*|CB 20+rb |Shift Left Arithmetic|m=m*2 ||SLA (HL) | 15 | 2 | |CB 26 | | ||SLA (IX+N) | 23 | 4 | |DD CB XX 26 | | ||SLA (IY+N) | 23 | 4 | |FD CB XX 26 | | ||SRA r | 8 | 2 |**0P0*|CB 28+rb |Shift Right Arith. |m=m/2 ||SRA (HL) | 15 | 2 | |CB 2E | | ||SRA (IX+N) | 23 | 4 | |DD CB XX 2E | | ||SRA (IY+N) | 23 | 4 | |FD CB XX 2E | | |+-------------+----+---+------+------------+---------------------+----------------------+|SLL r | 8 | 2 |**0P0*|CB 30+rb |Shift Left Logical* |m={0,m,CY}<- ||SLL (HL) | 15 | 2 | |CB 36 | | (SLL instructions ||SLL (IX+N) | 23 | 4 | |DD CB XX 36 | | are Unsupported) ||SLL (IY+N) | 23 | 4 | |FD CB XX 36 | | ||SRL r | 8 | 2 |**0P0*|CB 38+rb |Shift Right Logical |m=->{0,m,CY} ||SRL (HL) | 15 | 2 | |CB 3E | | ||SRL (IX+N) | 23 | 4 | |DD CB XX 3E | | ||SRL (IY+N) | 23 | 4 | |FD CB XX 3E | | |+-------------+----+---+------+------------+---------------------+----------------------+|SUB r | 4 | 1 |***V1*|90+rb |Subtract |A=A-s ||SUB N | 7 | 2 | |D6 XX | | ||SUB (HL) | 7 | 1 | |96 | | ||SUB (IX+N) | 19 | 3 | |DD 96 XX | | ||SUB (IY+N) | 19 | 3 | |FD 96 XX | | |+-------------+----+---+------+------------+---------------------+----------------------+|XOR r | 4 | 1 |***P00|A8+rb |Logical Exclusive OR |A=Axs ||XOR N | 7 | 2 | |EE XX | | ||XOR (HL) | 7 | 1 | |AE | | ||XOR (IX+N) | 19 | 3 | |DD AE XX | | ||XOR (IY+N) | 19 | 3 | |FD AE XX | | |#-------------+----+---+------+------------+---------------------+----------------------#[[Category:Hardware]][[Category:Programming]][[Category:Datasheet]][[Category:CPC Internal Components]]