output_wire <= output_wire_mem;
VHDL can be synthetised (compiled) into [[FPGA ]] chip. Two families of [[FPGA ]] chips exists : Xilinx (Diligent starter-kits are really fun and instructive) and Altera (cheaper). You cannot really compare them, units are not the same between them...
VHDL is more strict than Verilog, Verilog is more C language like. Verilog seems more used in America and VHDL in Europe. But you can plug them components together using drawn schematics.