* VRAM read/write via registers, 0,1,2 and 3,4,5 and port 0 use *logical* addresses and not physical addresses. Writing in one mode, and then reading back in another can yield different data because the addresses are translated from physical to logical based on the mode.
=== Interrupts ===
* Powergraph generates a maskable interrupt on CPC.
=== LOP ===