* Reading from the Kanji ROM ports without a Kanji ROM returns databus values
=== Ports and registers === * If a command doesn't require data to be read or written then reading from P#2 will cause /WAIT to be asserted to the Z80. * Status (Port #5) is readable always regardless of if soft reset is active or not. * Control (Port #7) is writable always regardless of soft reset is active or not. * MCS bit in Port #7 is always writable and the value is always readable through status "MCS" bit. This is documented. Soft reset state doesn't have any effect.
* Reading from the write only ports (or unused ports) returns databus values.
* The bits in the interrupt port (#6) are always set. An interrupt request to the Z80 will only be triggered if the interrupt is enabled in register R#9.
* If a command transfers data, and it expects data to be written (e.g. LMMC) to the command data port (P#2), then you can't use a read of the command data port to clear the data request. It must be a write. Similarly, if a command requests data to be read (e.g. LMCM) then you can use a write to the command data port to clear the data request.
=== Registers ===
* If you read from a write-only register you will see data-bus value because the V9990 doesn't assert data on the bus.
* Some registers have additional bits which are not documented. The mask describes which bits are read/write and which are unchanged.
Where the mask has a '1' bit, this bit is read/write. Where the mask has a '0' bit this bit remains at 0 and can't be changed.
- Register 7 (SCREEN MODE): Mask is &FF.
- Register 9 (INTERRUPT READ/WRITE): Mask is &87
- Register 15 (BACK DROP COLOR): Mask is &FF
- Register 22 (SCROLL CONTROL): Mask is &C1
- Register 25 (SPRITE PATTERN GENERATOR TABLE BASE ADDRESS): Mask is &CF
- Register 26 (LCD CONTROL): Mask is &FF
- Register 27 (PRIORITY CONTROL): Mask is &FF
* VRAM read/write via registers, 0,1,2 and 3,4,5 and port 0 use *logical* addresses and not physical addresses. Writing in one mode, and then reading back in another can yield data in a different order because the addresses are translated from logical to physical based on the mode.
* Register index is masked with &3f. This means reading "register 64" is the same as reading register 0.
=== Palette ===
* Palette red data has a mask of &9F (bits red and color key bit), blue and green have a mask of 0x01f.
LD A,&FF
OUT (C),A ;; palette index will be 1, and ternary counter is 0.
* If a command transfers data, and it requests data to be written to the command data port, then you can't use a read of this port to clear the data request. It must be a write. Similarly, if a command requests data to be read then you can use a write to clear the data request.
* If you read from a write-only register you will see data-bus value because the V9990 doesn't assert data on the bus.
* Some registers have additional bits which are not documented. The mask describes which bits are read/write and which are unchanged.
Where the mask has a '1' bit, this bit is read/write. Where the mask has a '0' bit this bit remains at 0 and can't be changed.
- Register 7 (SCREEN MODE): Mask is &FF.
- Register 9 (INTERRUPT READ/WRITE): Mask is &87
- Register 15 (BACK DROP COLOR): Mask is &FF
- Register 22 (SCROLL CONTROL): Mask is &C1
- Register 25 (SPRITE PATTERN GENERATOR TABLE BASE ADDRESS): Mask is &CF
- Register 26 (LCD CONTROL): Mask is &FF
- Register 27 (PRIORITY CONTROL): Mask is &FF
* VRAM read/write via registers, 0,1,2 and 3,4,5 and port 0 use *logical* addresses and not physical addresses. Writing in one mode, and then reading back in another can yield data in a different order because the addresses are translated from logical to physical based on the mode.
* Register index is masked with &3f. This means reading "register 64" is the same as reading register 0.
=== Interrupts ===