Difference between revisions of "Talk:Z80 STI RS232 interface"
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Your interpretation of the schematic in Note 2 is also incorrect. The combination of the 74LS138 followed by the 74LS20 means that the STI is mapped to ANY/ALL of the four lower addresses decoded from the 3 Address pins at the input. This is of course required for the circuit to function properly and definitely NOT nonsense to avoid legal issues as you suggest. | Your interpretation of the schematic in Note 2 is also incorrect. The combination of the 74LS138 followed by the 74LS20 means that the STI is mapped to ANY/ALL of the four lower addresses decoded from the 3 Address pins at the input. This is of course required for the circuit to function properly and definitely NOT nonsense to avoid legal issues as you suggest. | ||
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| + | :Bryce, my interpretation in Note 2 is EXACTLY the same as what you are saying. It maps to ALL four addresses. | ||
| + | :Thus, the decoding of the "lower" two addressbits (A2,A3) is total nonsense, really. --[[User:Nocash|Nocash]] 19:15, 10 May 2010 (UTC) | ||
Revision as of 15:15, 10 May 2010
The symbol in the Schematic for the 74LS20 is incorrect (Should be a 4 input NAND gate).
Your interpretation of the schematic in Note 2 is also incorrect. The combination of the 74LS138 followed by the 74LS20 means that the STI is mapped to ANY/ALL of the four lower addresses decoded from the 3 Address pins at the input. This is of course required for the circuit to function properly and definitely NOT nonsense to avoid legal issues as you suggest.
- Bryce, my interpretation in Note 2 is EXACTLY the same as what you are saying. It maps to ALL four addresses.
- Thus, the decoding of the "lower" two addressbits (A2,A3) is total nonsense, really. --Nocash 19:15, 10 May 2010 (UTC)
