As said above, the multiface watches the bus for writes to I/O ports, and memorizes the written values (required since most of the Gate Array and CRTC ports are write-only). Reading the memorized values is probably done via these I/O ports:
#FEE8 Multiface II - Enable Multiface II ROM/RAM (unknown functionW) #FEEA Multiface II - Disable Multiface II ROM/RAM (unknown functionW)The exact function of Writing any value to these registers is still unknown?I/O ports enables/disables the 8K ROM and 8K RAM in the Multiface. When enabled, the ROM/RAM are mapped to following addresses, 0000h-1FFFh Multiface ROM (including [[NMI]] vector at 0066h) 2000h-3FFFh Multiface RAMwith the internal ROM/RAM at 0000h-3FFFh in the CPC being disabled.
== Toolkit ==