===== Note =====
This function is not available in the Gate-Array, but is performed by a device at the same I/O port address location. In the CPC464, CPC664 and KC compact, this function is performed in a memory-expansion (e.g. Dk'Tronics 64K RAM Expansion), if this expansion is not present then the function is not available. In the CPC6128, this function is performed by a [[PAL16L8|PAL ]] located on the main PCB, or a memory-expansion. In the 464+ and 6128+ this function is performed by the ASIC or a memory expansion. Please read the document on RAM management for more information.
== Register 0 - Palette Index (Pen selection) ==
== Register 3 - RAM Banking ==
This register exists only in CPCs with 128K RAM (like the CPC 6128, or CPCs with [[Standard Memory Expansions]]). Note: In the CPC 6128, the register is a separate [[PAL16L8|PAL ]] that assists the Gate Array chip.
{|{{Prettytable|width: 700px; font-size: 2em;}}
| 6 || 1
|-
| 5 || - b || rowspan="3" |not used (or 64K bank for number (0..7); always 0 on an unexpanded CPC6128, 0-7 on [[Standard Memory Expansions]])
|-
| 4 || -b
|-
| 3 || -b
|-
| 2 || x || rowspan="3" | RAM Config (0..7)
The 3bit RAM Config value is used to access the total second 64K of the total 128K RAM (RAM Banks 0-7) that is built into the CPC 6128or the additional 64K-512K of standard memory expansions. These contain up to eight 64K ram banks, which are selected with bit 3-5. A standard CPC 6128 only contains bank 0. Normally the register is set to 0, so that only the first 64K RAM are used (identical to the CPC 464 and 664 models). The register can be used to select between the following eight predefined configurations only:
-Address- 0 1 2 3 4 5 6 7
0000-3FFF RAM_0 RAM_0 '''RAM_4 ''' RAM_0 RAM_0 RAM_0 RAM_0 RAM_0 4000-7FFF RAM_1 RAM_1 '''RAM_5 ''' '''RAM_3 ''' '''RAM_4 ''' '''RAM_5 ''' '''RAM_6 ''' '''RAM_7''' 8000-BFFF RAM_2 RAM_2 '''RAM_6 ''' RAM_2 RAM_2 RAM_2 RAM_2 RAM_2 C000-FFFF RAM_3 '''RAM_7 ''' '''RAM_7 ''' '''RAM_7 ''' RAM_3 RAM_3 RAM_3 RAM_3
The Video RAM is always located in the first 64K, VRAM is in no way affected by this register.
To display a CPC image you will need to use a analogue monitor with a composite sync.
=== Palette sorted by Hardware Color Colour Numbers ===
{| class="FCK__ShowTableBorders"
|}
=== Palette sorted by Firmware Color Colour Numbers ===
{| class="FCK__ShowTableBorders"
100% => add 2
=== Green Screen Colours ===
On a green screen (where all colours are shades of green), the colours (in the software/firmware colours), are in order of increasing intensity. Black is very dark, and white is bright green, and colour 13 is a medium green. (Thanks to [[Mark Rison|Mark Rison]] for this information)
== Pictures ==
<gallery>
Image:40010_am2_metal.jpg|40010 GA Metal Layer
Image:40010_am2_acid.jpg|40010 GA with Metal Layer removed
Image:40226_am4_metal.jpg|40226 PreASIC Metal Layer
</gallery>
==See also==
*[[Synchronising with the CRTC and display]] : technical details on the relationship between Gate Array and CRTC.
*[[Media:40010-simplified V03.pdf]] [https://www.cpcwiki.eu/forum/amstrad-cpc-hardware/gate-array-decapped!/msg170713/#msg170713 Forum thread] Gate Array schematics - reverse engineered by Gerald == External links ==* [https://www.grimware.org/doku.php/documentations/devices/gatearray Gate Array documentation from Grimware]* [http://quasar.cpcscene.net/doku.php?id=assem:gate_array Quasar Gate Array documentation (in french)] [[Category:Hardware]][[Category:Programming]][[Category:Datasheet]][[Category:Graphic]][[Category:CPC Internal Components]][[Category:Electronic Component]]