Because that can auto-generate bad unwanted sub-clocks...
If you know more than me about sequencing clocks with XilinxIn fact, it's DCM better to create each CLK and Altera's PPL not(making a true clock sequence without auto-generate unwanted sub-clockCLK)from DCM, do post on [http:in this case you enter in time constraints, and rules//mamevhdlchecks are done on every _edge instruction.wordpressChoosing only one sort of _edge (rising or falling) seems better also.com/2013/09/21/Using that way you just have more "bad compiling error" shown, helping you creating a better code. It seems also better (to create each CLK and not(CLK) from DCM) in order to solve the "magic" ramb16_s16_s16 component time equations (two differents clocksin entry of this component are making a certain clock equation solved automatically by common DCM -device/ MameVHDL : CLOCKS device].smaller common divisor)
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