Starter kit use only one RAM physical component for RAM ROM and DSK, so I had to manage accesses (it is possible in fact because Z80 is a sequential processor)
My clock take 4 wires, in fact it exists a clock sequence [[#Clock_sequence]] (during 1 z80 tic, I do several thinkthings). Perhaps I have to explain a few about this point of view.
RAM is done for being dump