end if
Because that can auto-generate bad unwanted sub-clocks...
==== Mirror VRAM ====
In order to get a better external RAM performance, and getting more luck about porting my project into others FPGA platform, I do now use a "Mirror VRAM" : external is just used by Z80 read and write. And a write in video RAM zone (like "poke &C000,255") does just write also in another parallel RAM, a FPGA internal RAM, that I call VRAM, as it is an FPGA internal RAM it can be written at a certain speed and read at another.
=== Clock sequence : version 2 ===