Changes

FPGAmstrad

53 bytes added, 16:16, 20 October 2017
/* Instruction timing : talk about r005.8.16c20 */
Have to check also the moment IO_ACK is taken into account during M1 signal (I think it's at begin of it, but have to re-check that)
 
===== RET cc and WAIT_n timing analysis =====
(wip)
=== Test of a real Zilog 80 ===
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