HALT is the only one instruction that will be always OK on plustest.dsk instruction timing testbench. As this instruction cannot be timed.
plustest.dsk testbench 5 does pass, except for two instruction : CPIR and CPDR - btw, in r005.8.16, its instructions are using then same "WAIT_n generator" slower than CPI/CPD : none (no WAIT_n added for theses instructions)
==== GA: WAIT_n generator - plustest.asm ====