== DESCRIPTION ==
The [[AY]]-3-8910/8912/8913 Programmable Sound Generator (PSG) is a LSI Circuit which can produce a wide variety of complex sounds under software control. The AY-3-8910/8912/8913 is manufactured in the General Instrument N-Channel Ion Implant Process. Operation requires a single +5V power supply, a TTL compatible clock, and a microprocessor controller such as the General Instrument 16-bit CP1610 or one of the PIC1650 series of 8-bit microcomputers.
The PSG is easily interfaced to any bus orientation system, its flexibility makes it useful in applications such as music synthesis, sound effects generation, audible alarms, tone signalling and FSK modems. The analog sound outputs can each provide 4bits of logarithmic digital to analog conversion greatly enhancing the dynamic range of the sounds produced.
|colspan=4|NOT USED||TP11||TP10||TP9||TP8||TP7||TP6||TP5||TP4||TP3||TP2||TP1||TP0
|-
|colspan=4| ||colspan=12|12-bit Tone Period (TP) to Tone Generator
|}
{|{{Prettytable|width: 700px; font-size: 2em;}}
|-
|'''R6'''||'''B7'''||'''B6'''||'''B5'''||'''B4'''||'''B3'''||'''B2'''||'''B1'''||'''B0'''
|-
|colspan=3|NOT USED||colspan=5|5-bit Noise Period (NP) to Noise Generator
|colspan=3|NOT USED||M||L3||L2||L1||L0
|-
|colspan=3| ||amplitude "mode"||cospancolspan=4|4-bit "fixed" amplitude level
|}
* Exceeding these ratings could cause permanent damage to the device. This is a stress rating only and functional operation of the devices at these conditions is not implied -- operating ranges are specified in Standard Conditions. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Data labelled " typical" is presented for design guidance only and is not guaranteed.
'''Storage Conditions (unless otherwise noted):'''
Vcc = ± 5V ±5%
Operating Temperature = 0°C to +70°C
{|{{Prettytable|width: 700px; font-size: 2em;}}
|'''Characteristics'''||'''Min'''||'''Sym'''||'''Max'''||'''Units'''||'''Conditions'''
|-
|'''DC CHARACTERISTICS'''
|-
|'''All inputs'''
|-
|Low level||Vil||0||0.7||V
|-
|High level||Vih||2.2||Vcc||V
|-
|'''All Outputs (except Analog Channel Outputs'''
|-
|Low level||Vol||0||0.4||V||1||TTL||Load
|-
|High level||Voh||2.4||Vcc||V||+100pf
|-
|'''Analog Channel Outputs'''||Vo||0||2000||uA||Test Curcuit: Fig 6
|-
|'''Power Supply Current'''||Icc||-||85||mA
|-
|'''AC CHARACTERISTICS'''
|-
|'''Clock Input'''||Fig 7.
|-
|Frequency||fc||1||2.5||MHz
|-
|Rise Time||tr||-||50||ns
|-
|Fall Time||tf||-||50||ns
|-
|Duty Cycle||-||40||60||%
|-
|'''Bus Signals (BDIR,BC2,BC1)'''
|-
|Associative Delay Time||tao||-||50||ns
|-
|'''Reset'''||Fig. 8
|-
|Reset Pulse Width||trw||5||-||us
|-
|Reset to Bus Control Delay Time||trb||100||-||ns
|-
|'''A9, A8, DA7--DA0 (Address Mode)'''||Fig 9
|-
|Address Setup Time tas 300 - ns
|-
|Address Hold Time tah 50 - ns
|-
|DA7--DA0 (Write Mode)'''||Fig. 10
|-
|Write Data Pulse Width||tdw||1800||-||ns
|-
|Write Data Setup Time||tds||50||-||ns
|-
|Write Data Hold Time||tdh||100||-||ns
|-
|'''DA7--DA0 (Read Mode)'''||Fig. 11
|-
|Read Data Access Time||tda||-||350||ns
|-
|'''DA7--DA0 (Inactive Mode)'''
|-
|Tristate Delay Time||tts||-||400||ns
|}
Characteristics Min Sym Max Units Conditions
DC CHARACTERISTICS
All inputs
Low level Vil 0 0.7 V
High level Vih 2.2 Vcc V
All Outputs (except Analog Channel Outputs
Low level Vol 0 0.4 V 1 TTL Load
High level Voh 2.4 Vcc V +100pf
Analog Channel Outputs Vo 0 2000 uA Test Curcuit: Fig 6
Power Supply Current Icc - 85 mA
AC CHARACTERISTICS
Clock Input Fig 7.
Frequency fc 1 2.5 MHz
Rise Time tr - 50 ns
Fall Time tf - 50 ns
Duty Cycle - 40 60 %
Bus Signals (BDIR,BC2,BC1)
Associative Delay Time tao - 50 ns
Reset Fig. 8
Reset Pulse Width trw 5 - us
Reset to Bus Control Delay Time trb 100 - ns
A9, A8, DA7--DA0 (Address Mode) Fig 9
Address Setup Time tas 300 - ns
Address Hold Time tah 50 - ns
DA7--DA0 (Write Mode) Fig. 10
Write Data Pulse Width tdw 1800 - ns
Write Data Setup Time tds 50 - ns
Write Data Hold Time tdh 100 - ns
DA7--DA0 (Read Mode) Fig. 11
Read Data Access Time tda - 350 ns
DA7--DA0 (Inactive Mode) '''Fig 7. CLOCK AND BUS SIGNAL TIMING'''
Tristate Delay Time tts - 400 ns '''Fig 8. RESET TIMING'''
'''Fig 79. CLOCK AND BUS SIGNAL LATCH ADDRESS TIMING'''
'''Fig 810. RESET WRITE DATA TIMING'''
'''Fig 911. LATCH ADDRESS READ DATA TIMING'''
Fig 10. WRITE DATA TIMING==Links==
Fig 11. READ DATA TIMING[[AY|AY's page with less specific subjects]]
[[Category:HardwareElectronic Component]] [[Category:Datasheet]][[Category:Music and sound|*]][[Category:CPC Internal Components]]