Changes

The [[AY]]-3-8910/8912/8913 Programmable Sound Generator (PSG) is a LSI Circuit which can produce a wide variety of complex sounds under software control. The AY-3-8910/8912/8913 is manufactured in the General Instrument N-Channel Ion Implant Process. Operation requires a single +5V power supply, a TTL compatible clock, and a microprocessor controller such as the General Instrument 16-bit CP1610 or one of the PIC1650 series of 8-bit microcomputers.

|colspan=4| ||colspan=12|12-bit Tone Period (TP) to Tone Generator

|'''R6'''||'''B7'''||'''B6'''||'''B5'''||'''B4'''||'''B3'''||'''B2'''||'''B1'''||'''B0'''

|cospancolspan=3|||amplitude "mode"||cospancolspan=4|4-bit "fixed" amplitude level

{|{{Prettytable|width: 700px; font-size: 2em;}}|colspan=8|'''Envelope Coarse Tune Register R14 '''||colspan=8|'''Envelope Fine Tune Register R13 '''|-|B7 ||B6 ||B5 ||B4 ||B3 ||B2 ||B1 ||B0 ||B7 ||B6 ||B5 ||B4 ||B3 ||B2 ||B1 ||B0 |-|EP15 ||EP14 ||EP13 ||EP12 ||EP11 ||EP10 ||EP9 ||EP8 ||EP7 ||EP6 ||EP5 ||EP4 ||EP3 ||EP2 ||EP1 ||EP0 |-|colspan=16|16-bit Envelope Period (EP) to Envelope Generator |}

{|{{Prettytable|width: 700px; font-size: 2em;}}|B7 ||B6 ||B5 ||B4 ||B3 ||B2 ||B1 ||B0 |-|colspan=4|NOT USED ||Hold ||Alternate ||Attack ||Continue |-|colspan=4| ||colspan=4|Function (To Envelope Generator) |} == I/O Port Data Store (Registers R16, R17) ==

== D/A Converter Operation== 

Fig 1. ENVELOPE SHAPE/CYCLE OPERATION{|{{Prettytable|width: 700px; font-size: 2em;}}|colspan=4|R15 Bits ||rowspan=3|GRAPHICAL REPRESENTATION OF ENVELOPE GENERATOR OUTPUT (E3 E2 E1 E0) |-|B3 ||B2 ||B1 ||B0 |-|Continue ||Attack ||Alternate ||Hold |-|0 ||0 ||x ||x ||[[Image:psg1.gif]]|-|0 ||1 ||x ||x ||[[Image:psg3.gif]] |-|1 ||0 ||0 ||0 ||[[Image:psg5.gif]] |-|1 ||0 ||0 ||1 ||[[Image:psg1.gif]] |-|1 ||0 ||1 ||0 ||[[Image:psg8.gif]] |-|1 ||0 ||1 ||1 ||[[Image:psg4.gif]] |-|1 ||1 ||0 ||0 ||[[Image:psg6.gif]] |-|1 ||1 ||0 ||1 ||[[Image:psg2.gif]] |-|1 ||1 ||1 ||0 ||[[Image:psg7.gif]] |-|1 ||1 ||1 ||1 ||[[Image:psg3.gif]]|-|colspan=4| ||[[Image:psg15.gif]] |}

'''Fig 2. DETAIL OF TWO CYCLES Of Fig 1 (ref. waveform "1010" in Fig.1)''' [[Image:psg9.gif]]

'''Fig 3. D/A CONVERTER OUTPUT''' '''Fig 4. SINGLE TONE WITH ENVELOPE SHAPE/CYCLE PATTERN 1010''' '''Fig 5. MIXTURE OF THREE TONES WITH FIXED AMPLITUDE''' == ELECTRICAL CHARACTERISTICS (AY-3-8910, AY-3-8912)== 

* Exceeding these ratings could cause permanent damage to the device. This is a stress rating only and functional operation of the devices at these conditions is not implied -- operating ranges are specified in Standard Conditions. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Data labelled " typical" is presented for design guidance only and is not guaranteed.  '''Storage Conditions (unless otherwise noted):''' 

 {|{{Prettytable|width: 700px; font-size: 2em;}}|'''Characteristics '''||'''Sym '''||'''Min '''||'''Typ** '''||'''Max '''||'''Units '''||'''Conditions '''|-|'''DC CHARACTERISTICS '''|-|'''All inputs '''|-|Low level ||Vil ||0 ||- ||0.6 ||V |-|High level ||Vih ||2.4 ||- ||Vcc ||V |-|'''All Outputs (except Analog Channel Outputs '''|-|Low level ||Vol ||0 ||- ||0.5 ||V ||Iol = 1.6mA, 20pF |-|High level ||Voh ||2.4 ||- ||Vcc ||V ||Ioh = 100uA, 20pF |-|Analog Channel Outputs ||Vo ||0 ||- ||60 ||dB ||Test Curcuit: Fig 6 |-|Power Supply Current ||Icc ||- ||45 ||85 ||mA |-|'''AC CHARACTERISTICS '''|-|'''Clock Input '''||Fig 7. |-|Frequency ||fc ||1 ||- ||2 ||MHz |-|Rise Time ||tr ||- ||- ||50 ||ns |-|Fall Time ||tf ||- ||- ||50 ||ns |-|Duty Cycle ||- ||25 ||50 ||85 ||% |-|'''Bus Signals (BDIR,BC2,BC1) '''|-|Associative Delay Time ||tao ||- ||- ||50 ||ns |-|'''Reset '''Fig. 8 |-|Reset Pulse Width ||trw ||500 ||- ||- ||ns |-|Reset to Bus Control Delay Time ||trb ||100 ||- ||- ||ns |-|'''A9, A8, DA7--DA0 (Address Mode) '''||Fig 9 |-|Address Setup Time ||tas ||400 ||- ||- ||ns |-|Address Hold Time ||tah ||100 ||- ||- ||ns |-|'''DA7--DA0 (Write Mode) '''||Fig. 10 |-|Write Data Pulse Width ||tdw ||500 ||- ||10,000 ||ns |-|Write Data Setup Time ||tds ||50 ||- ||- ||ns |-|Write Data Hold Time ||tdh ||100 ||- ||- ||ns |-|'''DA7--DA0 (Read Mode) '''||Fig. 11 |-|Read Data Access Time ||tda ||- ||250 ||500 ||ns |-|'''DA7--DA0 (Inactive Mode) '''|-|Tristate Delay Time ||tts ||- ||100 ||200 ||ns |} 

 '''Storage Conditions (unless otherwise noted):''' 

{|{{Prettytable|width: 700px; font-size: 2em;}}|'''Characteristics '''||'''Min '''||'''Sym '''||'''Max '''||'''Units '''||'''Conditions '''|-|'''DC CHARACTERISTICS '''|-|'''All inputs '''|-|Low level ||Vil ||0 ||0.7 ||V |-|High level ||Vih ||2.2 ||Vcc ||V |-|'''All Outputs (except Analog Channel Outputs '''|-|Low level ||Vol ||0 ||0.4 ||V ||1 ||TTL ||Load |-|High level ||Voh ||2.4 ||Vcc ||V ||+100pf |-|'''Analog Channel Outputs '''||Vo ||0 ||2000 ||uA ||Test Curcuit: Fig 6 |-|'''Power Supply Current '''||Icc ||- ||85 ||mA |-|'''AC CHARACTERISTICS '''|-|'''Clock Input '''||Fig 7. |-|Frequency ||fc ||1 ||2.5 ||MHz |-|Rise Time ||tr ||- ||50 ||ns |-|Fall Time ||tf ||- ||50 ||ns |-|Duty Cycle ||- ||40 ||60 ||% |-|'''Bus Signals (BDIR,BC2,BC1) '''|-|Associative Delay Time ||tao ||- ||50 ||ns |-|'''Reset '''||Fig. 8 |-|Reset Pulse Width ||trw ||5 ||- ||us |-|Reset to Bus Control Delay Time ||trb ||100 ||- ||ns |-|'''A9, A8, DA7--DA0 (Address Mode) '''||Fig 9 |-|Address Setup Time tas 300 - ns |-|Address Hold Time tah 50 - ns |-|DA7--DA0 (Write Mode) '''||Fig. 10 |-|Write Data Pulse Width ||tdw ||1800 ||- ||ns |-|Write Data Setup Time ||tds ||50 ||- ||ns |-|Write Data Hold Time ||tdh ||100 ||- ||ns |-|'''DA7--DA0 (Read Mode) '''||Fig. 11 |-|Read Data Access Time ||tda ||- ||350 ||ns |-|'''DA7--DA0 (Inactive Mode) ''' |-|Tristate Delay Time ||tts ||- ||400 ||ns |}  '''Fig 7. CLOCK AND BUS SIGNAL TIMING''' '''Fig 8. RESET TIMING''' '''Fig 9. LATCH ADDRESS TIMING''' '''Fig 10. WRITE DATA TIMING''' '''Fig 11. READ DATA TIMING''' ==Links== [[AY|AY's page with less specific subjects]]