* ''This is adapted from an article about the "Cathode Ray Tube Controller" hardware unit of the Amstrad by CPC. For the cpc scene member see [[ChaRleyTroniC]]''
== DISPTMG ==
DISPTMG signal defines the border. When DISPTMG is "1" the border colour is output by the Gate-Array to the display. The DISPTMG can be forced using R8 (DISPTMG Skew) on type 0,3 and 4 or by setting R6=0 on type 1. It is not possible to force the DISPTMG on type 2 or 5.
The border has higher priority than pixels but lower priority than the black colour output when HSYNC/VSYNC are active.
|''Register Index''||''Register Name''||''Range''||''CPC Setting''||''Notes''
|-
|0||Horizontal Total(-1)||00000000||63||Width of the screen, in characters. Should always be 63 (64 characters). 1 character == 1μs.
|-
|1||Horizontal Displayed||00000000||40||Number of characters displayed. Once horizontal character count (HCC) matches this value, DISPTMG is set to 1.
|-
|2||Horizontal Sync Position||00000000||46||When to start the HSync signal.
|-
|3||Horizontal and Vertical Sync Widths||VVVVHHHH||128+14||HSync pulse width in characters (0 means 16 on some CRTC), should always be more than 8; VSync width in scan-lines. (0 means 16 on some CRTC. Not present on all CRTCs, fixed to 16 lines on these)
|-
|4||Vertical Total(-1)||x0000000||38||Height of the screen, in characters.
|-
|5||Vertical Total Adjust||xxx00000||0||Measured in scanlines, can be used for smooth vertical scrolling on CPC.
|6||Vertical Displayed||x0000000||25||Height of displayed screen in characters. Once vertical character count (VCC) matches this value, DISPTMG is set to 1.
|-
|7||Vertical Sync positionPosition||x0000000||30||When to start the VSync signal, in characters.
|-
|8||Interlace and Skew||xxxxxx00||0||00: No interlace; 01: Interlace Sync Raster Scan Mode; 10: No Interlace; 11: Interlace Sync and Video Raster Scan Mode
|-
|9||Maximum Raster Address(aka Scan Line) (-1)||xxx00000||7||Maximum scan line address on CPC can hold between 0 and 7, higher values' upper bits are ignored
|-
|10||Cursor Start Raster||xBP00000||0||Cursor not used on CPC. B = Blink On/Off; P = Blink Period Control (Slow/Fast). Sets first raster row of character that cursor is on to invert.
{|{{Prettytable|width: 700px; font-size: 2em;}}
|rowspan=2|''Register Index''||rowspan=2|''Register Name''||colspan=43|''Type''
|-
|0||1||& 2||3||& 4
|-
|0||Horizontal Total(-1)||Write Only|colspan=3 style="text-align: center;"|Write Only||Write Only||(note 2)||(note 3)
|-
|1||Horizontal Displayed||Write Only|colspan=3 style="text-align: center;"|Write Only||Write Only||(note 2)||(note 3)
|-
|2||Horizontal Sync Position||Write Only|colspan=3 style="text-align: center;"|Write Only||Write Only||(note 2)||(note 3)
|-
|3||Horizontal and Vertical Sync Widths||Write Only|colspan=3 style="text-align: center;"|Write Only||Write Only||(note 2)||(note 3)
|-
|4||Vertical Total(-1)||Write Only|colspan=3 style="text-align: center;"|Write Only||Write Only||(note 2)||(note 3)
|-
|5||Vertical Total Adjust||Write Only|colspan=3 style="text-align: center;"|Write Only||Write Only||(note 2)||(note 3)
|-
|6||Vertical Displayed||Write Only|colspan=3 style="text-align: center;"|Write Only||Write Only||(note 2)||(note 3)
|-
|7||Vertical Sync positionPosition||Write Only|colspan=3 style="text-align: center;"|Write Only||Write Only||(note 2)||(note 3)
|-
|8||Interlace and Skew||Write Only|colspan=3 style="text-align: center;"|Write Only||Write Only||(note 2)||(note 3)
|-
|9||Maximum Raster Address(aka Scan Line) (-1)||Write Only|colspan=3 style="text-align: center;"|Write Only||Write Only||(note 2)||(note 3)
|-
|10||Cursor Start Raster||Write Only||Write Only||Write Read Only||(note 2)||(note 3)
|-
|11||Cursor End Raster||Write Only||Write Only||Write Read Only||(note 2)||(note 3)
|-
|12||Display Start Address (High)||Read/Write||Write Only||Write Only||Read/Write (note 2)||(note 3)
|-
|13||Display Start Address (Low)||Read/Write||Write Only||Write Only||Read/Write (note 2)||(note 3)
|-
|14||Cursor Address (High)||Read/Write|colspan=3 style="text-align: center;"|Read/Write||Read/Write||Read/Write (note 2)||(note 3)
|-
|15||Cursor Address (Low)||Read/Write|colspan=3 style="text-align: center;"|Read/Write||Read/Write||Read/Write (note 2)||(note 3)
|-
|16||Light Pen Address (High)||Read Only|colspan=3 style="text-align: center;"|Read Only||Read Only||Read Only (note 2)||(note 3)
|-
|17||Light Pen Address (Low)||Read Only|colspan=3 style="text-align: center;"|Read Only||Read Only||Read Only (note 2)||(note 3)
|-
|}
'''Notes'''
1. * On type 0 and 1, if a Write Only register is read from, "0" is returned.
2* CRTC type 4 is the same as CRTC type 3. See The registers also repeat as they do on the document "Extra CPC Plus Hardware Information" for more detailstype 3.
3. CRTC type 4 is * See the same as CRTC type 3. The registers also repeat as they do on the type 3document "Extra CPC Plus Hardware Information" for more details.
=== Horizontal and Vertical Sync (R3) ===
UM6845:
Bits 7..4 define Vertical Sync Width. If 0 is programmed this gives 16 lines of VSYNC.
Bits 3..0 define Horizontal Sync Width. If 0 is programmed no HSYNC is generated.
UM6845R:
Bits 7..4 are ignored. Vertical Sync is fixed at 16 lines.
Bits 3..0 define Horizontal Sync Width. If 0 is programmed no HSYNC is generated.
MC6845:
Bits 7..4 are ignored. Vertical Sync is fixed at 16 lines.
Bits 3..0 define Horizontal Sync Width. If 0 is programmed this gives a HSYNC width of 16.
Pre-ASIC/ASIC:
Bits 7..4 define Vertical Sync Width. If 0 is programmed this gives 16 lines of VSYNC.
Bits 3..0 define Horizontal Sync Width. If 0 is programmed this gives a HSYNC width of 16.
=== Interlace and Skew (R8) === UM6845:Bits 7..6 define the delay of the CUDISP signal.Bits 5..4 define the delay of the DISPTMG signal.Bits 3..2 are ignored.Bits 1..0 define the interlace mode. UM6845R:Bits 7..2 are ignored.Bits 1..0 define the interlace mode. MC6845:Bits 7..2 are ignored.Bits 1..0 define the interlace mode. Pre-ASIC/ASIC:Bits 7..6 are ignored.Bits 5..4 define the delay of the DISPTMG signal.Bits 3..2 are ignored.Bits 1..0 define the interlace mode. [[File:CRTC Interlace modes.png]] === UM6845R and R31 ===
R31 is described in the UM6845R documentation as "Dummy Register".
In the UM6845R it appears to have no effect. Reading and writing does nothing. Reading it returns 0x0ff.
R31 doesn't exist on types 0,2,3,4.
=== UM6845R and R12/R13 ===
The UM6845R differs to other CRTC in respect of R12/R13.
In demos to make a display compatible with all CRTCs program R12/R13 when VCC!=0. This will then take effect at the next frame start.
=== UM6845R status register ===
The UM6845R has a status register that can be read using port &BExx.
All the other bits read as 0 and don't have any function.
=== ASIC/Pre-ASIC and R10/R11 ===
The cursor raster registers R10/R11 act as status registers on Types 3 & 4.
{| class="wikitable sortable"
! R10 - Bit number
! Bit value
! Event
|-
|0
|1
|C0=R0
|-
|1
|0
|C0=R0/2
|-
|2
|0
|C0=R1-1 (if R0>=R1)
|-
|3
|0
|C0=R2
|-
|4
|0
|C0=R2+R3
|-
|5
|0
1
|R3h>0 : C0=0..R0 on the line R3h from Vsync (C4=R7)
R3h=0 : C0=0..R0 over 15 lines from Vsync (C4=R7)
|-
|6
|1
|Always 1
|-
|7
|0
0
|C0=0..R0-1 : VMA.Lsb=0xFF
C0=R0 : VMA'.Lsb=0x00 (same cond if C0=R0=0)
|}
{| class="wikitable sortable"
! R11 - Bit number
! Bit value
! Event
|-
|0
|0
|C4=R4 and C9=R9 and C0=R0 : Last char of screen
|-
|1
|0
|C4=R6-1 and C9=R9 and C0=R0 : Last char displayed
|-
|2
|0
|C4=R7-1 and C9=R9 and C0=R0 : Last char before Vsync
|-
|3
|0/1
|Timer 16 CRTC frames
|-
|4
|1
|Always 1
|-
|5
|0
|C9=R9 : C0=0 to R0
|-
|6
|0
|Always 0
|-
|7
|1
|(C9=R9 and C0=R0) or (C9=0 and C0=0 to R0-1)
|}
<br>
== CRTC Type Detection ==
<pre>
10 MODE 1:' Reinitialize screen
20 OUT &BC00,31:IF INP(&BF00)=255 THEN PRINT"crtc 1":END
30 OUT &BC00,12:IF INP(&BF00)=0 THEN PRINT"crtc 2":END
40 OUT &BC00,20:IF INP(&BF00)=0 THEN PRINT"crtc 0":END
50 PRINT"crtc 3/4"
</pre>
<br>
== CRTC Timing Diagram ==
[[File:CRTC timing small.gif]]
<br>
== Internal Counters ==
{| class="wikitable sortable"
! Counter name
! Abbr
! Alternate name
|-
|Horizontal Character Counter
|HCC
|C0
|-
|Horizontal Sync Counter
|HSC
|C3l
|-
|Vertical Character Counter
|VCC
|C4
|-
|Vertical Sync Counter
|VSC
|C3h
|-
|Vertical Line Counter
|VLC
|C9
|-
|Vertical Total Adjust Counter
|VTAC
|C5 (or C9 on CRTCs 0/3/4)
|-
|Frame Counter
|FC
|''Used for interlace and CRTC cursor blinking''
|}
<br>
== Hitachi Block Diagram ==
[[File:CRTC Block Diagram.png]]
<br>
== UMC Block Diagram ==
[[File:UMC CRTC Block Diagram.png]]
<br>
== Motorola Block Diagram ==
[[File:Motorola CRTC Block Diagram.png]]
<br>
== Datasheets ==
* [[Media:hd6845.hitachi.pdf|HD6845S (Hitachi) (aka type 0)]]
* [[Media:Um6845.umcUM6845-UMC.pdf|UM6845 (UMC) (aka type 0)]]
* [[Media:Um6845r.umc.pdf|UM6845R (UMC) (aka type 1)]]
* [[Media:Mc6845.motorola.pdf|MC6845 (Motorola) (aka type 2)]] [[Media:Mc6845.pdf|Other datasheet version]]
* [[VHDL implementation of the 6845]] == Clones Unused clones ==
* [CM607P a Bulgarian clone made in Pravetz factory]
* [EF6845P by Thomson Semiconductors]
* [UM6845E by UMC]* [SY6845EA by Synertek]* [https://github.com/hoglet67/BeebFpga/blob/dev/src/common/mc6845.vhd BeebFpga] [https://github.com/MiSTer-devel/Amstrad_MiSTer/blob/master/rtl/UM6845R.v MiSTer] [https://opencores.org/websvn/filedetails?repname=System09&path=%2FSystem09%2Ftrunk%2Frtl%2FVHDL%2Fcrtc6845.vhd OpenCores] Verilog/VHDL implementations of the 6845
== Tools about CRTC ==
* [http://www.cpcwiki.eu/imgs/9/99/Elmar_Krieger-SPECIAL_EFFECTS.dsk some BASIC tools to detect CRTC types 0-1-2 and show some effects] by [[Elmar Krieger]] (DSK for Emulators)
* [[File:Shaker24Shaker25.dsk]] Shaker v2.4 5 - Suite of CRTC tests associated with the CPC CRTC compendium (many of them will not work correctly on emulators and that was the purpose of the tests, to help create more compatible emulation)
* [[File:Shaker addon.dsk]] Shaker Add-On (Pixel 1 Hard Scroll / Vertical Rupture all Crtc)
* [http://www.grimware.org/doku.php/documentations/devices/crtc CRTC documentation from Grimware]
* [http://quasar.cpcscene.net/doku.php?id=assem:crtc Quasar CRTC documentation (in french)]
* [httphttps://logoncpcrulez.systemfr/coding_CRTC-Paradox.freehtm Dossier CRTC (Gozeur/Paradox)]* [[Media:Dossier CRTC(Ramlaid Mortel).frpdf]] Les entrailles du CRTC* [https:/down/thecheshirec.at/tag/crtc6845/ Leçons CRTC (CheshireCat)]* [[Media:ACCC1.67-EN.pdf Amstrad Cpc CRTC Compendium]] [[FileMedia:ACCC1.67-EN compressedFR.pdf]] CPC CRTC Compendium - Latest (10/2023!!) document containing in-depth info about CRTC programming on CPC.
==Related pages==