CRTC generates the address, Gate-Array reads the data and converts it to pixels based on the current mode.
CRTC pins RA3 and , RA4 , MA10, MA11 are not connected on CPC.
== CUDISP == CUDISP signal defines the hardware cursor. CRTC pin CUDISP is not connected to the Gate Array, but so it has no effect on a barebone CPC or Plus machine. However, this signal is present on the expansion port (and . And it is used by the [[PlayCity]] and [[Play2CPC]] expansions).
== DISPTMG ==
The VSYNC is also modified before being sent to the monitor. It happens two lines* after the VSYNC from the CRTC and stay two lines (same cut rule if VSYNC is lower than 4). PAL (50Hz) does need two lines VSYNC_width, and 4us HSYNC_width.
Using CRTC1, CRTCs 1 and 2 have a fixed VSYNC width value 0 means a value of 16. VSYNC width can be configured with Register 3 on CRTCs 0, 3 and 4.
== The 6845 Registers ==
|2||Horizontal Sync Position ||00000000||46||When to start the HSync signal.
|-
|3||Horizontal and Vertical Sync Widths||VVVVHHHH||128+14||HSync pulse width in characters (0 means 16 on some CRTC), should always be more than 8; VSync width in scan-lines. (0 means 16 on some CRTC. Not present on all CRTCs, fixed to 16 lines on these)
|-
|4||Vertical Total (-1)||x0000000||38||Height of the screen, in characters.
=== ASIC/Pre-ASIC and R10/R11 ===
The cursor raster registers R10/R11 act as status registers when read on Types 3 & 4.
{| class="wikitable sortable"
* [[Media:Dossier CRTC(Ramlaid Mortel).pdf]] Les entrailles du CRTC
* [https://thecheshirec.at/tag/crtc6845/ Leçons CRTC (CheshireCat)]
* [[Media:ACCC1.78-EN.pdf]] [[Media:ACCC1.78-FR.pdf]] CPC CRTC Compendium - Latest (1004/20232024!) document containing in-depth info about CRTC programming on CPC.
==Related pages==