CRTC generates the address, Gate-Array reads the data and converts it to pixels based on the current mode.
CRTC pins RA3 and RA4 are not connected on CPC.
CRTC pin CUDISP is not connected to the Gate Array, but it is present on the expansion port (and used by the [[PlayCity]] and [[Play2CPC]] expansions).
== DISPTMG ==
|8||Interlace and Skew||xxxxxx00||0||00: No interlace; 01: Interlace Sync Raster Scan Mode; 10: No Interlace; 11: Interlace Sync and Video Raster Scan Mode
|-
|9||Maximum Raster Address (aka Number of Scan LineLines) (-1)||xxx00000||7||Maximum scan line address on CPC can hold between 0 and 7, higher values' upper bits are ignored
|-
|10||Cursor Start Raster||xBP00000||0||Cursor not used on CPC. B = Blink On/Off; P = Blink Period Control (Slow/Fast). Sets first raster row of character that cursor is on to invert.
|8||Interlace and Skew||colspan=3 style="text-align: center;"|Write Only
|-
|9||Maximum Raster Address (aka Number of Scan LineLines) (-1)||colspan=3 style="text-align: center;"|Write Only
|-
|10||Cursor Start Raster||Write Only||Write Only||Read Only
<br>
== CRTC Timing Diagram Diagrams ==[[File:CRTC Timing Diagram Rockwell.png]] <br>
[[File:CRTC timing small.gif]]
* [[Media:Um6845r.umc.pdf|UM6845R (UMC) (aka type 1)]]
* [[Media:Mc6845.motorola.pdf|MC6845 (Motorola) (aka type 2)]] [[Media:Mc6845.pdf|Other datasheet version]]
*[[Media:CRTC-5-HD6345.pdf|HD6345 (Hitachi) (aka type 5)]] Upgraded pin-compatible CRTC chip with advanced functionalities [https://thecheshirec.at/2024/05/07/un-crtc6345-sur-amstrad-cpc/ Upgrading the CPC to HD6345]
== Unused clones ==
* [UM6845E by UMC]
* [SY6845EA by Synertek]
* CRTC6545 (MOS, Rockwell, Synertek) is pin-compatible with the 6845 and only has minor differences
* [https://github.com/hoglet67/BeebFpga/blob/dev/src/common/mc6845.vhd BeebFpga] [https://github.com/MiSTer-devel/Amstrad_MiSTer/blob/master/rtl/UM6845R.v MiSTer] [https://opencores.org/websvn/filedetails?repname=System09&path=%2FSystem09%2Ftrunk%2Frtl%2FVHDL%2Fcrtc6845.vhd OpenCores] Verilog/VHDL implementations of the 6845