Aside from the BIOS EPROM, the [[Aleste 520EX]] contains five Translation PROMs and EPROMs. They aren't accessible as memory to the CPU, but rather used to translate an as "logic look-up tables", translating incoming signals (through address inputs) to to outgoing signals (through data outputs).
== Aleste COLDAT eprom (Gate Array Parameters and Upper ROM Bank) ==
Part A (when MAPMOD=0)
COLDAT Addr CPU Addr Content
0000..00FF: 5FFFh ? Not used (filled with incrementing values: 00h..FFh)
0100..013F: 7FFFh Gate Array 0 (palette index)
0140..017F: 7FFFh Gate Array 1 (palette data)
01C0..01FF: 7FFFh Gate Array 3 (rambank, etc.)
0200..02FF: DFFFh Upper ROM Bank
0300..03FF: FFFFh FABFh ? Ext Port (filled with incrementing values: 00h..FFh)
Part B (when MAPMOD=1)
0400..04FF: 5FFFh ? Not used (filled with incrementing values: 00h..FFhsame as MAPMODE=0)
0500..053F: 7FFFh Gate Array 0 (palette index) (same as MAPMODE=0)
0540..057F: 7FFFh Gate Array 1 (palette data) (other than MAPMODE=0)
05C0..05FF: 7FFFh Gate Array 3 (rambank, etc.) (same as MAPMODE=0)
0600..06FF: DFFFh Upper ROM Bank (same as MAPMODE=0)
0700..07FF: FFFFh FABFh ? Ext Port (filled with incrementing values: 00h..FFhsame as MAPMODE=0)
Address 7FFFh: Gate Array 0: (A13=1, A15=0, DataIn=00h..3Fh) palette index
0100: 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F ;-pen index 0110: 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F ;-border(only bit4 is relevant here) 0120: 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F ;? NCOLOR4\same of above 0130: 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F ;? NCOLOR4/(but, with bit5 set, which has no function)
Address 7FFFh: Gate Array 1: (A13=1, A15=0, DataIn=40h..7Fh) palette data
When MAPMOD=0
0570: 03 13 23 33 07 17 27 37 0B 1B 2B 3B 0F 1F 2F 3F ;/
Address 7FFFh: Gate Array 2: (A13=1, A15=0, DataIn=80h..BFh) vmode, rom, leds
0180: 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F;\just a 1:1 translation, 0190: 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F; increasing values 00h..3Fh 01A0: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF; (but, with bit7=set=blah) 01B0: B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF;/
Address 7FFFh: Gate Array 3: (A13=1, A15=0, DataIn=C0h..FFh) ram bank,
01C0: 80 81 82 83 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F ;\basically incrementing
01D0: 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F ; values 00h..3Fh, but
01E0: 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F ; with bit7=1 =VRAMACC in first 01F0: 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F ;/first four values
Address DFFFh: Upper ROM Bank: (A13=0, A15=1)
0200..0207: 01 01 01 03 01 01 01 02 ;\translates bank 03h to 3 (menu), bank
0208..02FF: filled with 01 ;/07h to 2 (amsdos), others to 1 (basic)
Address FABFh: Ext Port
0300..03FF: filled with incrementing values: 00h..FFh
== Aleste MAPPER prom (Gate Array 3, RAM banking) ==
Inputs:
A0..A8 9bit scanline counter (clocked by 3CY aka 1M div sth, reset by HY aka VSYNC) A9 clocked by HSYNC period (duration counted as 1M div sth8 or so)
A10 not used (wired to GND)
Outputs:
0200..03FF: Same as 0000h..01FFh, but with D0 inverted
(ie. "A A F B B B A A 8 8 8 8 8 8 8 8" etc.)
(that is, SYNC is inverted during HSYNC period)
* Note: The "." entries contain a value of 9. (The "." is just used instead of "9" to make the other entries more visible)
07E0: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
07F0: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
[[Category:Non CPC Computers]][[Category:Clones]]