The Aside from the BIOS EPROM, the [[Aleste 520EX]] contains five Translation PROMs and EPROMs. They aren't connected accessible as memoryto the CPU, but rather to translate an used as "logic look-up tables", translating incoming signals (through address inputs) to to outgoing signals (through data bitsoutputs).
== Aleste COLDAT eprom (Gate Array Parameters and Upper ROM Bank) ==
Inputs:
A0..A7 Databus D0..D7
A8 CPU A13
A9 CPU A15
A10 MAPMOD ;affects ONLY the palette bits in COLDAT
Outputs: (enabled only when /IORQ=Low)
D0..D5 XD0..XD5
D6 Not used (not connected)
D7 VRAMACC
Part A (when MAPMOD=0) COLDAT Addr CPU Addr Content 0000..00FF: 5FFFh ? Not used (filled with incrementing values: 00h..FFh) 0100..013F: 7FFFh Gate Array 0 (palette index) 0140..017F: 7FFFh Gate Array 1 (palette data) 0180..01BF: 7FFFh Gate Array 2 (vmode, rom, leds) 01C0..01FF: 7FFFh Gate Array 3 (rambank, etc.) 0200..02FF: DFFFh Upper ROM Bank 0300..03FF: FFFFh FABFh ? Ext Port (filled with incrementing values: 00h..FFh) Part B (when MAPMOD=1) 0400..04FF: 5FFFh ? Not used (filled with incrementing values: 00h..FFhsame as MAPMODE=0) 0500..053F: 7FFFh Gate Array 0 (palette index) (same as MAPMODE=0) 0540..057F: 7FFFh Gate Array 1 (palette data) (other than MAPMODE=0) 0580..05BF: 7FFFh Gate Array 2 (vmode, rom, leds) (same as MAPMODE=0) 05C0..05FF: 7FFFh Gate Array 3 (rambank, etc.) (same as MAPMODE=0) 0600..06FF: DFFFh Upper ROM Bank (same as MAPMODE=0) 0700..07FF: FFFFh FABFh ? Ext Port (filled with incrementing values: 00h..FFhsame as MAPMODE=0)
Address 7FFFh: Gate Array 0: (A13=1, A15=0, DataIn=00h..3Fh) palette index
0100: 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F ;-pen index 0110: 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F ;-border(only bit4 is relevant here) 0120: 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F ;? NCOLOR4\same of above 0130: 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F ;? NCOLOR4/(but, with bit5 set, which has no function)
Address 7FFFh: Gate Array 1: (A13=1, A15=0, DataIn=40h..7Fh) palette data
When MAPMOD=0
0140: 15 15 1C 1F 10 13 14 17 13 1F 0F 3F 03 33 07 37 ;\27-color palette 0150: 10 1C 0C 3C 00 30 04 34 11 1D 0D 3D 01 31 05 35 ; 27-color palette/ 0160: 15 15 1C 1F 10 13 14 17 13 1F 0F 3F 03 33 07 37 ;\27-color palette (same as above)
0170: 10 1C 0C 3C 00 30 04 34 11 1D 0D 3D 01 31 05 35 ;/
When MAPMOD=1
0570: 03 13 23 33 07 17 27 37 0B 1B 2B 3B 0F 1F 2F 3F ;/
Address 7FFFh: Gate Array 2: (A13=1, A15=0, DataIn=80h..BFh) vmode, rom, leds
0180: 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F;\just a 1:1 translation, 0190: 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F; increasing values 00h..3Fh 01A0: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF; (but, with bit7=set=blah) 01B0: B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF;/
Address 7FFFh: Gate Array 3: (A13=1, A15=0, DataIn=C0h..FFh) ram bank,
01C0: 80 81 82 83 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F ;\basically incrementing
01D0: 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F ; values 00h..3Fh, but
01E0: 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F ; with bit7=1 =VRAMACC in first 01F0: 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F ;/first four values
Address DFFFh: Upper ROM Bank: (A13=0, A15=1)
0200..0207: 01 01 01 03 01 01 01 02 ;\translates bank 03h to 3 (menu), bank
0208..02FF: filled with 01 ;/07h to 2 (amsdos), others to 1 (basic)
Address FABFh: Ext Port
0300..03FF: filled with incrementing values: 00h..FFh
== Aleste MAPPER prom (Gate Array 3, RAM banking) ==
This 256x4bit PROM assists Gate Array 3 (RAM banking)
Inputs: A0..A1 CPU A14..A15 ;-the addressed 16K memory block A2..A5,A7 M0..M4 A6 MAPMOD Outputs: D0..D3 MAP14..MAP17
Addresses used when MAPMOD=0:
0060: 8 8 8 8 9 9 9 9 A A A A B B B B ;
0070: C C C C D D D D E E E E F F F F ;/
00C0: 0 0 0 0 1 1 1 1 2 2 2 2 3 3 3 3 ;\second 256K 00D0: 4 4 4 4 5 5 5 5 6 6 6 6 7 7 7 7 ; second 256K(fifth bit is handled elsewhere: bit4 is ANDed 00E0: 8 8 8 8 9 9 9 9 A A A A B B B B ; (fifth bit stored elsewhere?with MAPMOD and then passed to MAP18 directly)
00F0: C C C C D D D D E E E E F F F F ;/
Allows to map any bank to any location (similar to the RAM "mappers" in MSX
This 256x4bit PROM assists Gate Array 2 (RAM/ROM enable)
Inputs: A0 PROM0 ;\from gate array (but translated via COLDAT, A1 PROM1 ;/ not the original value written by the CPU) A2 CPU A14 ;\the addressed 16K memory block A3 CPU A15 ;/ A4 CPU A0 A5 /MREQ A6 /RD A7 RAMDIS ;-RAMDIS pin on expansion port Outputs: D0 BUFFER0 ? ;set LOW on read from even RAM address (16bit-to-8bit bus) D1 BUFFER1 ? ;set LOW on read from odd RAM address (16bit-to-8bit bus) D2 /ROMEN ;ROM enable (note: ROMDIS is handled elsewhere) D3 /RAMEN ;RAM enable
Page: 0000h 4000h 8000h C000h
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0000: B 6 B 6 6 6 6 6 6 6 6 6 B B 6 6 ;even addresses 0010: B 5 B 5 5 5 5 5 5 5 5 5 B B 5 5 ;odd addresses 0020: F F F F F F F F F F F F F F F F ;\inactive because /MREQ=high 0030: F F F F F F F F F F F F F F F F ;/ 0040: F F F F F F F F F F F F F F F F ;\inactive because /RD=high 0050: F F F F F F F F F F F F F F F F ;/ 0060: F F F F F F F F F F F F F F F F ;\inactive because /MREQ=high and /RD=high 0070: F F F F F F F F F F F F F F F F ;/ 0080: B 7 B 7 7 7 7 7 7 7 7 7 B B 7 7 ;\ 0090: B 7 B 7 7 7 7 7 7 7 7 7 B B 7 7 ; same as above, but BUFFER0 and BUFFER1 bits all SET 00A0: F F F F F F F F F F F F F F F F ; (reading from internal RAM forcefully disabled via 00B0: F F F F F F F F F F F F F F F F ; RAMDIS signal from expansion port) 00C0: F F F F F F F F F F F F F F F F ; (however WRITING to RAM isn't disabled, the "7" means 00D0: F F F F F F F F F F F F F F F F ; signal /RAMEN=LOW, so writing is possible) 00E0: F F F F F F F F F F F F F F F F ; 00F0: F F F F F F F F F F F F F F F F ;/
== Aleste VDKEY eprom (video and keyboard) ==
This 2Kx8bit EPROM is used for Video and Keyboard translation.
Inputs: A0..A8 9bit scanline counter (clocked by 3CY aka 1M div sth, reset by HY aka VSYNC) A9 clocked by HSYNC period (duration counted as 1M div sth8 or so)
A10 not used (wired to GND)
Outputs:
D0 video SYNC* (hsync+vsync, passed to monitor SYNC)
D1 video HY* (vsync, passed to ppi)
01C0..01DF: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
01E0..01FF: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Note: The "." entries contain a value of 9.(The "." is just used instead of "9" to make the other entries more visible)
0200..03FF: Same as 0000h..01FFh, but with D0 inverted
(ie. "A A F B B B A A 8 8 8 8 8 8 8 8" etc.)
(that is, SYNC is inverted during HSYNC period)
* Note: The "." entries contain a value of 9. (The "." is just used instead of "9" to make the other entries more visible)
----
Upper Data bits in VDKEY (the Keyboard related part):
0000..001F: E D D F F F F 6 C C D E E D E 5 E 9 E 9 D C D 2 C F B A 8 E F 5
0020..003F: F F B B A A C 4 8 8 A B E 9 A 4 9 9 B C A A B 5 8 9 9 B C A A 4
0040..005F0057: 9 9 8 B 9 B C 6 A A A A A A B 5 8 8 8 8 8 F E 7 F F F F F F F F 00600058..01FF: Filled with "F"
0200..021F: 7 6 7 0 3 2 1 1 9 2 0 0 3 2 2 1 4 9 6 A 3 0 9 1 3 8 A 6 2 8 7 8
0220..023F: 9 A 8 6 9 5 5 A A 9 4 3 9 2 7 6 8 7 7 7 8 2 9 A 6 5 6 4 4 A 3 8
0240..025F0257: 3 4 1 2 1 5 1 A 0 0 0 0 0 0 1 5 3 4 5 7 8 5 5 6 0258..03FF: Filled with "F F F F F F F F"
0260..03FF: Filled with "F"----
Upper and Lower Data Bits in Unused Part of VDKEY:
07E0: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
07F0: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
[[Category:Non CPC Computers]][[Category:Clones]]