=== Gate Array Register 3 ===
?In the CPC register 3 was not handled by the Gate-Array. The 16L8 PAL IC was also mapped at the same I/O address as the Gate-Array and bit 7 and 6 of the data had to be 1 to avoid conflict with other Gate-Array registers. In the Aleste register 3 is effectively Mapper select. Writing to port #7Fxx with bit 7 and bit 6 of data set to 1 can be used to set page 3 RAM bank in Aleste mapper mode, or to define CPC RAM configuration in CPC mode.
== Upper ROM Bank ==