Changes

In fact, it's better to create you clock sequencer wiring each CLK and not(CLK) directly from DCM, in this case you enter in time constraints norm, and then rules/checks are done on every _edge instruction. Choosing only one sort of _edge (rising or falling) seems better also. Using that way you just have more "bad compiling error" shown, helping you creating a better code.

It seems also better (to create each CLK and not(CLK) from DCM) in order to solve the Clock sequence using "magic" ramb16_s16_s16 component time equations (two differents clocks in entry of this component are making counter plugged with a certain clock equation solved automatically by common DCM - smaller common divisor algorithm (just take a little look at final resulting generated clocks after compilation (in result summary))) Clock sequence " was in fact out of law (but running fine in my first versions of FPGAmstrad as I'm a good blind developer), because output are not under clock constraint : just think about that a "not" component added just after a clock wire is out of law... destroying "time constraint" solver (the one telling you when your code is bad (can be better))