Three new memory mapped registers have been added within the ASIC, to provided a horizontally split screen facility. One at address 6801h defines the scan line after which the screen split occurs. A value of zero (as at power on reset) will turn this feature off.
The other register pair at 6802h and 6803h define the start address in memory to show for the split.
The screen can be split multiple times in a single frame by reprogramming 6801h, 6802 and 6803h.
The other register pair at 6802h and 6803h define address takes the start address in memory (same number form as R12 and R13 respectively in of the 6845, and (e.g. &3000 being for the split to start at &c000). Any CRTC address can be used (the split may therefore scroll). 6802h is the high byte first) which partly represents of the location in memory from which to start displaying data for address and 6803h is the lower screen (low byte of the address.The full byte address that is displayed is defined by the soft scroll register, 6845's internal scan line counter and the split screen start programmed address). This value The programmed address is read stored when the 6845's Horizontal counter matches Horizontal Displayed (R1) on the line programmed. This value It is then stored to be used loaded into 6845's MA counter on the next lineafter. Note that because the address is loaded into MA it effects the rest of the screen until the next time it is re-programmed or the display restarts.
This feature allows the lower part of the picture to come from a separate memory area and be separately scrolled. The start address is loaded into 6845's MA counter on the line after. Note that because the address is loaded into MA it effects the rest of the screen unless a new split screen value is programmed.
Note that care should be taken with programming this facility such that the screen split does not alter the function of address bits A1-A8 and the dynamic memory refresh is not upset. This can be accomplished by setting the start of the second screen to lie on 16k boundary. The reason is that the dynamic memory refresh is derived from the memory address that the 6845 describes.