1=Right Justify (A0 from AD0)
0 Reset (Caution: If set, requires a 3rd write to resurrect)
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* Control Register 01h - Master Configuration Control Register (R/W)
2 PAE Port A Enable
0-1 LC Counter/Timer Link Controls (see below)
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* Counter/Timer Link Controls values are:
2=Counter/Timer 1's /OUTPUT does Trigger Counter/Timer 2
3=Counter/Timer 1's /OUTPUT is Counter/Timer 2's Count Input
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* Control Register 20h - Port A Mode Specification Register (R/W)
0 LTM Latch on Pattern Match (in Bit Mode), or
0 DTE Deskew Timer Enable (in Handshake Modes)
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* Control Register 21h - Port A Handshake Specification Register (R/W)
4=Special Req, 5=Input Request, 7=Output Request)
2-0 Deskew Time (MSBs of Deskew Timer Time Constant, LSB is forced 1)
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* Control Register 08h - Port A Command and Status Register (Parts R/W)
5 IP Interrupt Pending (Read Only)
4 ERR Interrupt Error (Read Only)
* For Port A/B Registers:
3 ORE Output Register Empty (Read Only)
2 IRF Input Register Full (Read Only)
1 PMF Pattern Match Flag (Read Only)
0 IOE Interrupt on Error
* For Counter/Timer Registers:
3 RCC Read Counter Control (Read/Set Only - cleared by reading CCR LSB)
2 GCB Gate Command Bit
1 TCB Trigger Command Bit (Write Only) (Read returns 0)
0 CIP Counter in Progress (Read Only)
* Set/Clear Command List:
0=Null Code, 1=Clear IP & IUS
2=Set IUS, 3=Clear IUS
4=Set IP, 5=Clear IP
6=Set IE, 7=Clear IE
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* Control Register 22h - Data Path Polarity Register Port A (R/W)
* Control Register 05h - Data Path Polarity Register Port C (4 LSBs only) (R/W)
7-0 DPP Data Path Polarity bits (0=Non-inverting, 1=Inverting)
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* Control Register 23h - Data Direction Register Port A (R/W)
* Control Register 06h - Data Direction Register Port C (4 LSBs only) (R/W)
7-0 DD Data Direction bits (0=Output Bit, 1=Input Bit)
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* Control Register 24h - Special I/O Control Register Port A (R/W)
7-0 SIO Special Input/Output bits (0=Normal Input or Output,
1=Output with open drain, or Input with 1's catcher)
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* Control Register 0Dh - Port Data Register Port A (R/W) (directly addressable)
* Control Register 0Eh - Port Data Register Port B (R/W) (directly addressable)
7-0 Data Bits7-0 (usually 0=Low, 1=High, unless Polarity is inverted)
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* Control Register 0Fh - Port Data Register Port C (R/W) (directly addressable)
7-4 Lock Bits3-0 (0=Writing Enabled, 1=Writing Inhibited)(Read returns 1)
3-0 Data Bits3-0 (usually 0=Low, 1=High, unless Polarity is inverted)
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* Control Register 25h - Port A Pattern Polarity (PP) Register (R/W)
1 1 0 One-to-Zero Transition (falling edge)
1 1 1 Zero-to-One Transition (raising edge)
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* Control Register 1Ch - Counter/Timer 1 Mode Specification (R/W)
2 REB Retrigger Enable
1-0 DCS Output Duty Cycle Select (0=Pulse,1=OneShot,2=SquareWave,3=Reserved)
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* Control Register 10h - Counter/Timer 1 Current Count Register MSB (R)
* Control Register 15h - Counter/Timer 3 Current Count Register LSB (R)
7-0 CCR Current Count Register (Read Only) (8bits of 16bit total)
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* Control Register 16h - Counter/Timer 1 Time Constant Register MSB (R/W)
* Control Register 1Bh - Counter/Timer 3 Time Constant Register LSB (R/W)
7-0 TCR Time Constant Register (aka Reload value) (8bits of 16bit total)
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* '''Control Register 02h - Interrupt Vector Register Port A (R/W)'''
Port A/B: In Priority Encoded Vector Mode:
3-1 Number of highest Priority Bit with a match
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* '''Port A/B: In all other Modes:'''
3 Not auto-modified
2-1 Counter/Timer Number (0=C/T3, 1=C/T2, 2=C/T1, 3=Error)
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* '''Control Register 1Fh - Current Vector Register (R)'''
7-0 Interrupt Vector Based on highest priority unmasked IP (IP=int pending)
If no interrupt pending then all 1's are output (ie. register is FFh)