Clock sequence using '''counter plugged with a clock''' was in fact out of law (but running fine in my first versions of FPGAmstrad as I'm a good blind developer), because output are not under clock constraint : just think about that a "not" component added just after a clock wire is out of -time constraints- law... destroying "time constraint" solver (the one telling you when your code is bad (can be better), "time constraint" is last step of FPGA compiling process)
==== Clock sequence : Mirror mirror VRAM (performance) ====
In order to get a better external RAM performance, and getting more luck about porting my project into others FPGA platform, I do now use a "Mirror VRAM" : external is just used by Z80 read and write (no more clock sequence finally ^^'). And a write in video RAM zone (like "poke &C000,255") does just write also in another parallel RAM, a FPGA internal RAM, that I call VRAM, this VRAM can be written at a certain speed and read at another for VGA purpose (FPGA internal RAM can be used like that)