end if
Because that can auto-generate bad unwanted sub-clocks...
=== Clock sequence : version 2 ===
In fact, it's better to create you clock sequencer '''wiring each CLK and not(CLK) directly from DCM''', in this case you enter in time constraints norm, and then rules/checks are done on every _edge instruction. Choosing only one sort of _edge (rising or falling) seems better also. Using that way you just have more "bad compiling error" shown, helping you creating a better code.