Changes

'''=== Instruction timing''' : ===I tested instruction timing of T80 compare to instruction timing of JavaCPC emulator. I deduce synchronization of Z80 with CRTC on M1 signal by WAIT_n insertion in order to have a multiple of 4 Tstates per instruction. I deduce also one WAIT_n inserted during MEM_WR operation (yes I log testbench T80, i'm crazy)

'''Test I just made a testbench log of a real Zilog 80''T80 (log of instruction's M1, in fact the only difference between T80 of opencore and real Z80 is first M1 coming after knowing that T80 run on rising_edgeI send a lot of NOP after my instruction), and Z80 run during low state. Test past with little modification of sequencer forcing compare it do nothing during low state of z80, resulting to a clockdown JavaCPC timing array. Some instructions was not tested (memory are too overclocked interrupt wait, and special timing (instructions with this sequencer modificationchange timing)), perhaps using buffer on address bus and data bus could solve this detail... but as it runs for me it is not a problemall others passed correctly.

'''Alignment === Test of HSYNC Interrupt''' : a button of starter kit display HSYNC interrupt loopback linesreal Zilog 80 ===[[File:Z80fx2bb.jpg]]Code name : Z80fx2bb, it's usefull to compare to a Maxam test that alternate color real Z80@2MHz (instead of 4MHz) on them fx2bb extension card.

For it I plug all wires simply from 1 to 40. Some wires are cut, somes are Vcc, others GND. Z80 output are directly connected, Z80 input are pullup with red-red-red resistors (I like red), Z80 is powered 5v (pmod can give 5v using jumper). In fact z80 is so old component that powering it 5v do output 3.3v. In fact the only difference between T80 of opencore and real Z80 is that T80 run on rising_edge, and Z80 run during low state. Test past with little modification of sequencer forcing it do nothing during low state of z80, resulting a clockdown (memory are too overclocked with this sequencer modification), perhaps using buffer on address bus and data bus could solve this detail... but as it runs for me it is not a problem. === Alignment of HSYNC Interrupt ===A button of starter kit display HSYNC interrupt loopback lines, it'''s useful to compare to a Maxam test that alternate color on them. === Sniffing of a real Amstrad''', ===[[File: cpc_plus_m1.jpg]]Code name : Raptor I listen to some wires of my Amstrad CPC 6128 plus, but I can't access VSYNC/HSYNC output of CRTC, so I have to buy another model in order to do this test. In fact you can listen at clock of Amstrad and transmit it to FPGA DCM component, resulting a accelerated clock sequence, that's it, with FPGA DCM you can overclock output Amstrad clock signal in order to insert more operations, I use this tip for listening signals and save them inside starter kit asynchronous RAM (write, stop write, write, stop write... i'm a perfectionist paranoid...)  You can power Amstrad CPC using extension port, applying 5v. By doing it, power down button of Amstrad don't run. Using this way you reach a common 5v power between starter-kit and Amstrad. I connected wires from extension port directly to FPGA, as they are used just for listening.