== 8255 Part numbers used in the CPC during it's its lifetime ==
* NEC D8255AC-2
== The 8255 in the CPC ==
The [[8255 PPI chip]] is a general purpose input/output IC. This document will describe it's its role in the Amstrad CPC, CPC+ and KC compact systems. To understand it's its full functions please read the datasheet.
In these systems it is connected to the AY-3-8912 Programmable Sound Generator (PSG), keyboard, cassette recorder, the VSYNC of the 6845 CRTC and the "busy" signal from the parallel port.
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In the CPC+Group Mode 1 (Strobed Input/Output) and Group Mode 2 (Bi-Directional Bus), the 8255 is integrated into the ASICas far as I know, are not used by any program. The "emulation" Group Mode 0 (Basic Input/Output) is not complete and some functionality is not available. Please see the "Extra CPC+ documentation" for more informationalways used.
* Mode 1 (Strobed Input/Output) and Mode 2 (Bi-Directional Bus)In the CPC+, as far as I know, are the 8255 is integrated into the ASIC. The "emulation" is not used by any program, Mode 0 (Basic Input/Output) complete and some functionality is always usednot available. Please see the [https://cpctech.cpcwiki.de/docs/cpcplus.html Extra CPC+ documentation] for more information.
== Port Usage ==
* LK1-4 are links on the mainboard ("0" bits are wired to GND). On CPC464,CPC664,CPC6128 and GX4000 they are labeled LK1-LK4, on the CPC464+ and CPC6128+ they are labeled LK101-LK103 (and LK104, presumably?).
* Bit5 (/EXP) can be used by a expansion device to report it's its presence. "1" = device connected, "0" = device not connected. This is not always used by all expansion devices. ''is it used by any expansions?'' [in the DDI-1 disc interface, /EXP connects to the ROM bank selection, bank 0 or bank 7] * If port B is programmed as an output, you can make a fake vsync visible to the Gate-Array by writing 1 to bit 0. You can then turn it off by writing 0 to bit 0. It is fake in the sense that it is not generated by the CRTC as it normally is. This fake vsync doesn't work on all CPCs. It is not known if it is dependent on CRTC or 8255 or both.
* For more info on LK1-LK4 (and further LKs) see [[LK Links]]
This register has two different functions depending on bit7 of the data written to this register.
=== PPI Control with Bit7=0 ===
If Bit 7 is "0" then the register is used to set or clear a single bit in Port C:
Bit 0 B New value for the specified bit (0=Clear, 1=Set)
Bit 1-3 N0,N1,N2 Specifies the number of a bit (0-7) in Port C
Bit 4-6 - Not Used
Bit 7 SF Must be "0" in this case
[[File:8255 Control0.png]]
=== PPI Control with Bit7=1 ===
If Otherwise, if Bit 7 is "1" then the other bits will initialize Port Group Modes and Ports A-B -Cupper-Clower as Input or Output:
Bit 0 IO-Cl Direction for Port C, lower bits (always 0=Output in CPC)
* In the CPC only Bit 4 is of interest, all other bits are always having the same value. In order to write to the PSG sound registers, a value of 82h must be written to this register. In order to read from the keyboard (through PSG register 0Eh), a value of 92h must be written to this register.
=== PPI Control with Bit7=0 ===Otherwise, if Bit 7 is "0" then the register is used to set or clear a single bit in Port C[[File:8255 Control1.png]]
Bit 0 == Group Modes == In some of these modes, port C is used as a control/status port for port A or B New value . It can be used to confirm when data transfer may take place, and reflect any other flags. The 8255 PPI is therefore supplied with the added option for the specified bit (user to set or reset any individual bits in port C. === Mode 0– Simple Input/output mode =Clear==In this mode, the ports can be used for simple I/O operations without handshaking signals. Port A, port B provide simple I/O operation. The two halves of port C can be either used together as an additional 8-bit port, or they can be used as individual 4-bit ports. Since the two halves of port C are independent, they may be used such that one-half is initialized as an input port while the other half is initialized as an output port. [[File:8255 - mode-0.png]] === Mode 1– Strobed Input/output or Handshake mode ===Set) Bit When we wish to use port A or port B for handshake (strobed) input or output operation, we initialise that port in mode 1-3 N0(port A and port B can be initialised to operate in different modes,N1i.e.,N2 Specifies for e.g., port A can operate in mode 0 and port B in mode 1). Some of the number pins of a bit port C function as handshake lines. For port B in this mode (0-7irrespective of whether is acting as an input port or output port) in Port C, PC0, PC1 and PC2 pins function as handshake lines. Bit 4If port A is initialised as mode 1 input port, then, PC3, PC4 and PC5 function as handshake signals. Pins PC6 and PC7 are available for use as input/output lines. [[File:8255 -6 mode- Not Used1.png]] Bit 7 SF Must === Mode 2 – Bidirectional Mode ===Only port A can be "initialized in this mode. Port A can be used for bidirectional handshake data transfer. This means that data can be input or output on the same eight lines (PA0 - PA7). Pins PC3 - PC7 are used as handshake lines for port A. The remaining pins of port C (PC0 - PC2) can be used as input/output lines if group B is initialized in mode 0" or as handshaking for port B if group B is initialized in mode 1. In this casemode, the 8255 may be used to extend the system bus to a slave microprocessor or to transfer data bytes to and from a floppy disk controller. Acknowledgement and handshaking signals are provided to maintain proper data flow and synchronisation between the data transmitter and receiver. [[File:8255 - mode-2.png]] === Port pins summary === [[File:8255 - Port pins.gif]]
== Programming Examples ==
LD E,&FF ;Data to put into port
OUT (C),A E ;Send to port A
;Return port I/O status and operating modes
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= Diagrams =
= Block Diagram = [[ImageFile:8255 ppi 1Block Diagram.jpgpng]] = Amstrad ASIC PPI = *The 8255 PPI is not emulated by the Pre-ASIC. These CPC’s have a real PPI chip and therefore behave like the first generation of CPC’s.*The ASIC PPI does not support Group Modes other than Groupe Mode 0.*On the ASIC PPI, Port B is always defined as input and Port C is always defined as output.*On a real PPI chip, when the PPI control register is used (with bit7=1) to configure the ports, the output latches of all ports are reset to 0. The ASIC poorly emulates the PPI and does not reset these ports.
[[Image:8255 ppi 2.jpg]]
= Resources =
* [[Media:Intel8255A_datasheet.pdf]] PPI Datasheet (Intel)
* [[Media:PPI M5L8255AP-5.pdf]] PPI Datasheet (Mitsubishi)
* [[VHDL https://github.com/jotego/jt8255 JT8255] Verilog implementation of the 8255 PIO]]PPI
= Links =
*[http://en.wikipedia.org/wiki/Intel_8255 Wikipedia about the 8255ppi]*[http://quasar.cpcscene.net/doku.php?id=assem:ppi Quasar PPI documentation (in french)]
[[Category:Electronic Component]][[Category:CPC Internal Components]][[Category:Programming]]