CRTC

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  • This is adapted from an article about the "Cathode Ray Tube Controller" by CPC scene member ChaRleyTroniC


The CRTC (Cathode Ray Tube Controller) helps to generate the video signal of the Amstrad CPC.

NOTE: This document describes the functionality in terms of the CPC with its separate CRTC and Gate-Array. The Plus has both integrated into the same IC, but could be considered to have two functional blocks, one for CRTC and one for Gate-Array. In this document the term 'Gate-Array' is used, but this also applies to the ASIC.

Overview

The 6845 Cathode Ray Tube Controller (CRTC) is a programmable IC used to generate video displays. This IC is used in a variety of computers including the Amstrad CPC, Amstrad CPC+ and KC Compact.

The CRTC was a common part available from many different manufacturers. During the life of the CPC, Amstrad sourced the CRTC from various manufacturers.

All ICs used were based on the same design but have a different implementation. As a result they do not operate identically in all situations. This document highlights these differences.

This table lists the known ICs used, with their part number, manufacturer and type number.

Part number Manufacturer Type number (note 3)
HD6845S Hitachi 0
UM6845 UMC 0
UM6845R UMC 1
MC6845 Motorola 2
AMS40489 Amstrad 3 (note 1)
40226 Amstrad 4 (note 2)

NOTES

1. The CRTC functionality is integrated into the CPC+ ASIC. This type exists only in the CPC464+,CPC6128+ and GX4000.

2. This type exists in "cost-down" CPC464 and CPC6128 systems. In the "cost-down" the CRTC functionality is integrated into a single ASIC IC. This ASIC is often refered to as the "Pre-ASIC" because it preceeded the CPC+ ASIC. The CRTC functionality of the Pre-ASIC is almost identical to the CRTC within the ASIC.

3. In the Amstrad community each 6845 implementation has been assigned a type number. This type identifies a group of implementations which operate in exactly the same way.

As far as I know, the type number system was originally used by demo programmers.

It is possible to detect the 6845 present using software methods, and this is done to:

  • warn that the software was not designed for the detected 6845 and may function incorrectly,
  • to adapt the software so that it will run with the detected 6845
  • In most cases, the type of the detected 6845 is reported.

4. As far as I know, the KC compact used HD6845R only.

Timings and relating with Z80 instructions count

Some informations like : how many Z80 instructions can I fit within a scan line ? Within a screen ? Etc... See http://www.cpcwiki.eu/forum/programming/frame-flyback-and-interrupts/msg25106/#msg25106 (To be extracted/edited to conform to wiki good practices).

Programming

The 6845 is selected when bit 14 of the I/O port address is set to "0". Bit 9 and 8 of the I/O port address define the function to access. The remaining bits can be any value, but it is adviseable to set these to "1" to avoid conflict with other devices in the system.

The recommended I/O port addresses are

I/O port address Function Read/Write
&BCxx Select 6845 register Write only
&BDxx Write 6845 register data Write only
&BExx (note 1) Read only
&BFxx (note 1) Read only

NOTE

1. The function of these I/O ports is dependant on the CRTC type

2. If you perform an IN instruction to the select or write functions it will write data to the CRTC from the current data on the bus.

Addressing

The following table defines the generated memory address from the CRTC and Gate-Array signals.

Memory Address Signal Signal source Signal name
A15 6845 MA13
A14 6845 MA12
A13 6845 RA2
A12 6845 RA1
A11 6845 RA0
A10 6845 MA9
A9 6845 MA8
A8 6845 MA7
A7 6845 MA6
A6 6845 MA5
A5 6845 MA4
A4 6845 MA3
A3 6845 MA2
A2 6845 MA1
A1 6845 MA0
A0 Gate-Array CCLK

CRTC generates the address, Gate-Array reads the data and converts it to pixels based on the current mode.

DISPTMG

DISPTMG signal defines the border. When DISPTMG is "1" the border colour is output by the Gate-Array to the display. The DISPTMG can be forced using R8 (DISPTMG Skew) on type 0,3 and 4 or by setting R6=0 on type 1. It is not possible to force the DISPTMG on type 2.

The border has higher priority than pixels but lower priority than the black colour output when HSYNC/VSYNC are active.

HSYNC and VSYNC

On CPC, HSYNC and VSYNC from the CRTC are passed into the Gate-Array.

When HSYNC is active Gate-Array outputs the palette colour black. If the HSYNC is set to 14 characters then black will be output for 14us.

The HSYNC is modified before being sent to the monitor. It happens 2us after the HSYNC from the CRTC and lasts 4us when HSYNC length is greater or equal to 6.

If R2=46, and HSYNC width is 14 then monitor hsync starts at 48 and lasts until 51.

On a CPC monitor, the HSYNC is rendered in "absolute black". It is darker than the black output by the Gate-Array.

The VSYNC is also modified before being sent to the monitor. It happens two lines* after the VSYNC from the CRTC and stay two lines (same cut rule if VSYNC is lower than 4). PAL (50Hz) does need two lines VSYNC_width, and 4us HSYNC_width.

Using CRTC1, VSYNC width value 0 means a value of 16.

The 6845 Registers

The Internal registers of the 6845 are:

Register Index Register Name Range CPC Setting Notes
0 Horizontal Total (-1) 00000000 63 Width of the screen, in characters. Should always be 63 (64 characters). 1 character == 1μs.
1 Horizontal Displayed 00000000 40 Number of characters displayed. Once horizontal character count (HCC) matches this value, DISPTMG is set to 1.
2 Horizontal Sync Position 00000000 46 When to start the HSync signal.
3 Horizontal and Vertical Sync Widths VVVVHHHH 128+14 HSync pulse width in characters (0 means 16 on some CRTC), should always be more than 8; VSync width in scan-lines. (0 means 16 on some CRTC. Not present on all CRTCs, fixed to 16 lines on these)
4 Vertical Total (-1) x0000000 38 Height of the screen, in characters.
5 Vertical Total Adjust xxx00000 0 Measured in scanlines, can be used for smooth vertical scrolling on CPC.
6 Vertical Displayed x0000000 25 Height of displayed screen in characters. Once vertical character count (VCC) matches this value, DISPTMG is set to 1.
7 Vertical Sync Position x0000000 30 When to start the VSync signal, in characters.
8 Interlace and Skew xxxxxx00 0 00: No interlace; 01: Interlace Sync Raster Scan Mode; 10: No Interlace; 11: Interlace Sync and Video Raster Scan Mode
9 Maximum Raster Address (aka Scan Line) (-1) xxx00000 7 Maximum scan line address on CPC can hold between 0 and 7, higher values' upper bits are ignored
10 Cursor Start Raster xBP00000 0 Cursor not used on CPC. B = Blink On/Off; P = Blink Period Control (Slow/Fast). Sets first raster row of character that cursor is on to invert.
11 Cursor End Raster xxx00000 0 Sets last raster row of character that cursor is on to invert
12 Display Start Address (High) xx000000 48
13 Display Start Address (Low) 00000000 0 Allows you to offset the start of screen memory for hardware scrolling, and if using memory from address &0000 with the firmware.
14 Cursor Address (High) xx000000 0
15 Cursor Address (Low) 00000000 0
16 Light Pen Address (High) xx000000 Read Only
17 Light Pen Address (Low) 00000000 Read Only

registers 18-31 read as 0, on type 0 and 2. registers 18-30 read as 0 on type1, register 31 reads as 0x0ff.

Details about Reg. 12 and Reg. 13 specifically: 

 .------- REG 12 --------.   .------- REG 13 --------.
 |                       |   |                       |
  15 14 13 12 11 10 09 08     07 06 05 04 03 02 01 00
 .--.--.--.--.--.--.--.--.   .--.--.--.--.--.--.--.--.
 |X |X |  |  |  |  |  |  |   |  |  |  |  |  |  |  |  |
 '--'--'--'--'--'--'--'--'   '--'--'--'--'--'--'--'--'
       '--.--'--.--'---------------.-----------------'
          |     |                  |
          |     |                  '------> Offset for setting
          |     |                           videoram 
          |     |                           (1024 positions)
          |     |                           Bits 0..9
          |     |
          |     '-------------------------> Video Buffer : note (1)
          |
          '-------------------------------> Video Page : note (2)
 note (1)                 note (2)
 .--.--.--------------.  .--.--.---------------.
 |11|10| Video Buffer |  |13|12|   Video Page  |
 |--|--|--------------|  |--|--|---------------|
 | 0| 0|     16Ko     |  | 0| 0|  0000 - 3FFF  |
 |--|--|--------------|  |--|--|---------------|
 | 0| 1|     16Ko     |  | 0| 1|  4000 - 7FFF  |
 |--|--|--------------|  |--|--|---------------|
 | 1| 0|     16Ko     |  | 1| 0|  8000 - BFFF  |
 |--|--|--------------|  |--|--|---------------|
 | 1| 1|     32Ko     |  | 1| 1|  C000 - FFFF  |
 '--'--'--------------'  '--'--'---------------'

So, it's possible to use 32KB screen size (used for overscan) by setting bits 11 and 10 both to 1 (of Register 12). Bits MA11 and MA10 of the address generated by the CRTC are not written on the address bus to access video memory; settings both bits to 1 is the only way to cause a carry to bit MA12 when address pass over the end of current video page to change the memory address to the next video page.

CRTC Differences

In this section I will attempt to identify all the differences between each CRTC.

The following tables list the functions that can be accessed for each type:

Type 0

b1 b0 Function Read/Write
0 0 Select internal 6845 register Write Only
0 1 Write to selected internal 6845 register Write Only
1 0 - -
1 1 Read from selected internal 6845 register Read only

Type 1

b1 b0 Function Read/Write
0 0 Select internal 6845 register Write Only
0 1 Write to selected internal 6845 register Write Only
1 0 Read Status Register Read Only
1 1 Read from selected internal 6845 register Read only

Type 2

b1 b0 Function Read/Write
0 0 Select internal 6845 register Write Only
0 1 Write to selected internal 6845 register Write Only
1 0 - -
1 1 Read from selected internal 6845 register Read only

Type 3 and 4

b1 b0 Function Read/Write
0 0 Select internal 6845 register Write Only
0 1 Write to selected internal 6845 register Write Only
1 0 Read from selected internal 6845 register Read Only
1 1 Read from selected internal 6845 register Read only

It is not possible to read from all the internal registers, this table shows the read/write status of each register for each type:

Register Index Register Name Type
0 1 & 2 3 & 4
0 Horizontal Total (-1) Write Only
1 Horizontal Displayed Write Only
2 Horizontal Sync Position Write Only
3 Horizontal and Vertical Sync Widths Write Only
4 Vertical Total (-1) Write Only
5 Vertical Total Adjust Write Only
6 Vertical Displayed Write Only
7 Vertical Sync Position Write Only
8 Interlace and Skew Write Only
9 Maximum Raster Address (aka Scan Line) (-1) Write Only
10 Cursor Start Raster Write Only Write Only Read Only
11 Cursor End Raster Write Only Write Only Read Only
12 Display Start Address (High) Read/Write Write Only Read/Write
13 Display Start Address (Low) Read/Write Write Only Read/Write
14 Cursor Address (High) Read/Write
15 Cursor Address (Low) Read/Write
16 Light Pen Address (High) Read Only
17 Light Pen Address (Low) Read Only

Notes

  • On type 0 and 1, if a Write Only register is read from, "0" is returned.
  • CRTC type 4 is the same as CRTC type 3. The registers also repeat as they do on the type 3.
  • See the document "Extra CPC Plus Hardware Information" for more details.

Horizontal and Vertical Sync (R3)

UM6845: Bits 7..4 define Vertical Sync Width. If 0 is programmed this gives 16 lines of VSYNC. Bits 3..0 define Horizontal Sync Width. If 0 is programmed no HSYNC is generated.

UM6845R: Bits 7..4 are ignored. Vertical Sync is fixed at 16 lines. Bits 3..0 define Horizontal Sync Width. If 0 is programmed no HSYNC is generated.

MC6845: Bits 7..4 are ignored. Vertical Sync is fixed at 16 lines. Bits 3..0 define Horizontal Sync Width. If 0 is programmed this gives a HSYNC width of 16.

Pre-ASIC/ASIC: Bits 7..4 define Vertical Sync Width. If 0 is programmed this gives 16 lines of VSYNC. Bits 3..0 define Horizontal Sync Width. If 0 is programmed this gives a HSYNC width of 16.

Interlace and Skew (R8)

UM6845: Bits 7..6 define the delay of the CUDISP signal. Bits 5..4 define the delay of the DISPTMG signal. Bits 3..2 are ignored. Bits 1..0 define the interlace mode.

UM6845R: Bits 7..2 are ignored. Bits 1..0 define the interlace mode.

MC6845: Bits 7..2 are ignored. Bits 1..0 define the interlace mode.

Pre-ASIC/ASIC: Bits 7..6 are ignored. Bits 5..4 define the delay of the DISPTMG signal. Bits 3..2 are ignored. Bits 1..0 define the interlace mode.

CRTC Interlace modes.png

UM6845R and R31

R31 is described in the UM6845R documentation as "Dummy Register".

Its use is described in the documentation for the Rockwell R6545 in combination with R18, R19 and R8 and the Status Register.

In the UM6845R it appears to have no effect. Reading and writing does nothing. Reading it returns 0x0ff.

R31 doesn't exist on types 0,2,3,4.

UM6845R and R12/R13

The UM6845R differs to other CRTC in respect of R12/R13.

When VCC=0, R12/R13 is re-read at the start of each line. R12/R13 can therefore be changed for each scanline when VCC=0.

Just like other CRTCs when RC==(R9-1), the current MA is captured for the next char-line.

In demos to make a display compatible with all CRTCs program R12/R13 when VCC!=0. This will then take effect at the next frame start.

UM6845R status register

The UM6845R has a status register that can be read using port &BExx.

Bit 6 is set to 1 if there is a strobe input to the /LPEN signal. It is cleared to 0 when either R17 or R16 (LPEN address) of the CRTC are read. It signals there is a valid LPEN input. On my CPC (arnoldemu) with UM6845R, it is triggered at power on, R17 and R16 have the values 0 when read.

Bit 5 is set to 1 when CRTC is in "vertical blanking". Vertical blanking is when the vertical border is active. i.e. VCC>=R6.

It is cleared when the frame is started (VCC=0). It is not directly related to the DISPTMG output (used by the CPC to display the border colour) because that output is a combination of horizontal and vertical blanking. This bit will be 0 when pixels are being displayed.

All the other bits read as 0 and don't have any function.

ASIC/Pre-ASIC and R10/R11

The cursor raster registers R10/R11 act as status registers on Types 3 & 4.

R10 - Bit number Bit value Event
0 1 C0=R0
1 0 C0=R0/2
2 0 C0=R1-1 (if R0>=R1)
3 0 C0=R2
4 0 C0=R2+R3
5 0

1

R3h>0 : C0=0..R0 on the line R3h from Vsync (C4=R7)

R3h=0 : C0=0..R0 over 15 lines from Vsync (C4=R7)

6 1 Always 1
7 0

0

C0=0..R0-1 : VMA.Lsb=0xFF

C0=R0 : VMA'.Lsb=0x00 (same cond if C0=R0=0)

R11 - Bit number Bit value Event
0 0 C4=R4 and C9=R9 and C0=R0 : Last char of screen
1 0 C4=R6-1 and C9=R9 and C0=R0 : Last char displayed
2 0 C4=R7-1 and C9=R9 and C0=R0 : Last char before Vsync
3 0/1 Timer 16 CRTC frames
4 1 Always 1
5 0 C9=R9 : C0=0 to R0
6 0 Always 0
7 1 (C9=R9 and C0=R0) or (C9=0 and C0=0 to R0-1)


CRTC Type Detection

10 MODE 1:' Reinitialize screen
20 OUT &BC00,31:IF INP(&BF00)=255 THEN PRINT"crtc 1":END
30 OUT &BC00,12:IF INP(&BF00)=0 THEN PRINT"crtc 2":END
40 OUT &BC00,20:IF INP(&BF00)=0 THEN PRINT"crtc 0":END
50 PRINT"crtc 3/4"


CRTC Timing Diagram

CRTC timing small.gif


Internal Counters

Counter name Abbr Alternate name
Horizontal Character Counter HCC C0
Horizontal Sync Counter HSC C3l
Vertical Character Counter VCC C4
Vertical Sync Counter VSC C3h
Vertical Line Counter VLC C9
Vertical Total Adjust Counter VTAC C5 (or C9 on CRTCs 0/3/4)
Frame Counter FC Used for interlace and CRTC cursor blinking


Hitachi Block Diagram

CRTC Block Diagram.png


UMC Block Diagram

UMC CRTC Block Diagram.png


Motorola Block Diagram

Motorola CRTC Block Diagram.png


Datasheets

Unused clones

  • [CM607P a Bulgarian clone made in Pravetz factory]
  • [EF6845P by Thomson Semiconductors]
  • [UM6845E by UMC]
  • [SY6845EA by Synertek]
  • BeebFpga MiSTer OpenCores Verilog/VHDL implementations of the 6845

Tools about CRTC

Links

Related pages

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