"Arnold V" Specification "Arnold V" Specification Issue 1.4 12th March 1990 Amstrad PLC (c) Copyright Amstrad plc PRODUCT RANGE - AMSTRAD HOME COMPUTERS 1) WHY THE NEW RANGE? The changing home computer market. Enhanced technology: Number of colours Sound quality Software media type Redesign cosmetic styling 2) THE 1990 RANGE Games console model number GX4000 464 PLUS built-in cassette and ROM cartridge 6128 PLUS built-in disk drive and ROM cartridge MM12 - monochrome 12" monitor CM14 - colour 14" monitor 3) MARKETING PACKS GX4000 Console Mains adaptor Paddle control unit x 2 Gift box 464 PLUS Computer 6128 PLUS Basic/* Game Cartridge Paddle Control unit Gift box * Free game to be advised 4) AVAILABILITY All products delivered by late August. 5) HOME COMPUTER PLUS RANGE SPECIFICATION GX4000 464+ 6128+ Processor Z80 Z80 Z80 Memory 64k 64k 128K Configuration ROM cartridge Cassette/ROM Cartridge 3" disk/ROM Cartridge Colours 32 from 4096 32 from 4096 32 from 4096 Softscroll * * * Splitscreen * * * Sprites 16 16 16 Sound Stereo ASG Stereo ASG Stereo ASG Joystick Ports: Digital x2 x2 x2 Analogue x1 x1 x1 Monitor Choice Mono/Colour Mono/Colour Mono/Colour 6) LAUNCH TIMETABLE Month Activity April Presentation to major customers in launch market May Production start up End June/July Press conference in Paris for leading home computer publicatons. maximum 10 Editors per market August Software available September Launch in all markets across specialist and consumer press. Volume supplies in retailers October Advertising in home computer/youth publications November/December Heavy-weight advertising - TV, National Press. CONTENTS 1 PRODUCT RANGE OVERVIEW 1.1 Common Features 1.2 Amstrad 464 Plus 1.3 Amstrad 6128 Plus 1.4 Further Variants 2 TECHNICAL SPECIFICATION 2.1 Hardware Sprites 2.2 Colour palette 2.3 Split Screen facility 2.4 Programmable Raster Interrupt 2.5 Soft scroll facility 2.6 Automatic feeding of sound generator 2.7 Vectored interrupts 2.8 Enhanced ROM cartridge support 2.9 Analogue paddle ports 2.10 PAL subcarrier locking 2.11 Locking of enhanced features 2.12 Eight-bit printer support 2.13 Floppy disc data separator 2.14 Power Requirements 3 SOFTWARE SPECIFICATION 3.1 6128 3.2 464 4 MECHANICAL SPECIFICATION 5 DISPLAY DEVICES 5.1 Monitors 5.2 Modulator/Power Supply units 6 NATIONAL VARIANTS 7 PACKING LIST APPENDIX I - New Register Map APPENDIX II - Connector pinouts 1 PRODUCT RANGE OVERVIEW This project will provide a more sophisticated and stylish replacement for the existing CPC464 and CPC6128 computers. This will be achieved by: o Redesigning the ASIC and main PCB to incorporate a number of new features o Restyling the casework to provide a more modern appearance. 1.1 Common Features The casework will consist of a new two piece set of plastic mouldings. This will contain a horizontally mounted, double-sided PCB assembly on which are mounted most of the electronics for the computer. A small, vertically mounted, daughter PCB will provide the connector for a ROM cartridge. Any size ROM cartridge from 16k x 8 up to 512k x 8 can be installed. The firmware, fitted to the main PCB on earlier CPC computers, is supplied in a ROM cartridge. All expansion and peripheral device connectors will be mounted on the main PCB. In addition to the connectors used on the existing CPC range, there will be: Separate connectors for the two joysticks, replacing the old daisy-chain arrangement. However, the daisy chain system can still be used on the Joystick 1 connector if required. An additional 15-way female D-type connector will provide four analogue input channels and access to the four existing "fire" buttons. This will be pin compatible with the games control port on the PC200 (PC-8) computer. All PCB edge connectors will be replaced by types that are easier to screen against spurious RF emission. The printer connector is a 25-way female D type, as used on the PC1640 etc, and the expansion connector is a 50-way Delta (Centronics style) type, as currently used in Germany. The 6128's TAPE socket will be replaced by a 6 pin RJ-11 type for the light gun. The computer will provide stereo sound via additional pins on the monitor connector, as well as from the stereo sound socket. All existing CPC electrical features will be provided, plus some new features. There will be complete backward compatibility except that: The border colour will be undefined at power-on reset The new 6128 version will have no tape socket The following new features will become available once a software "lock" has been opened, thus preventing existing CPC software from accidentally invoking them: There will be 16 Sprites, each consisting of 16x16 high resolution pixels, in fifteen colours separate from the main screen colours. Each sprite can be magnified in X or Y, moved around the screen, and turned on or off independent of the main screen. Sprite pixels can be transparent, and sprites have a fixed order of priority (i.e. "depth"), so that they can pass in front of each other, in front of the main screen, and behind the border. The colour palette will be extended to allow simultaneous display of up to 32 colours (16 main + 15 sprite + border) from a palette of 4096, rather than the current 17 from 27. Additional screen controls will be added, to allow split-screen operation and smooth scrolling to be used. An automated sound generation process will allow generation of more complex sound effects with greatly reduced software overhead. Some other internal features to ease implementation of better games software, described in the technical specification section. The functions of display monitor and power supply are provided by either: o A restyled range of monitors, consisting of a white tube monochrome monitor MM12 and an improved colour monitor CM14. o An MP2-style modulator/power supply unit. o A Peritel adaptor/power supply unit. The old CPC6128 keyboard is used, except that the colour scheme will be changed and the connecting cable will exit in a different location. 1.2 Amstrad 464 Plus This variant will have an integral cassette tape drive, and 64k bytes of dynamic RAM. It will be supplied with a ROM cartridge containing the system firmware plus the BASIC language, disk firmware and a game, although it is not possible to select the disk firmware. 1.3 Amstrad 6128 Plus This variant will have an integral 3" floppy disk drive (5V only) plus a 36-way Delta (Centronics style) expansion socket allowing a second 3" drive to be added. The 6128 Plus will be supplied with a ROM cartridge containing the system firmware plus the BASIC language, disk firmware and a game. 128k bytes of dynamic RAM will be fitted to the main PCB. 1.4 Further Variants Unlike the existing CPC range, the size of dynamic RAM and whether or not a disk drive is installed are separately configurable options. It is therefore possible to produce a "4128" (128k diskless) or "664" (64k with disk) variant. Also, it is possible to increase the number of analogue input channels to eight. 2 TECHNICAL SPECIFICATION The technical specification is essentially similar to the existing CPC 464/6128 range, with some enhancements. This specification should therefore be read in conjunction the "Amstrad CPC 6128 Software Interface Spec" Issue 2, 17th February 1985. New features will be added by changes to the ASIC and main PCB circuitry. The overriding concern in the specification of this new product range has been the need for total backward compatibility with the existing CPC range. Many of the new features within the ASIC employ new registers, which can be mapped to replace the page of RAM from 4000 to 7FFFh in the CPU memory map, by setting a bit pattern in an I/O port. Before this port is allowed to "exist", a deliberately obscure I/O sequence is needed. This mechanism protects existing software from accidents such as killing its own RAM page. The following new features are to be provided by changes to the ASIC device and the main PCB electronics: 2.1 Hardware Sprites Sixteen hardware sprites will be provided by the ASIC. Each will consist of an array of 16x16 pixels of four bits per pixel. A sprite pixel will be "transparent" when it has a value of zero, thus allowing 15 sprite colours. The sprite pixel data will exist in memory mapped registers within the ASIC, from address 4000h. The lower four bits of each byte will contain the data for a single pixel. The first 16 bytes contain the data for the upper scan line, starting at the top left hand corner of the sprite. 15 more similar scan lines of 16 pixels each will follow, thus each 256 (0100h) byte block of register space will contain one sprite. When the data for a sprite is read or written, that sprite will be removed from the display for the duration of the access. Thus sprite data should only be accessed during retraced time or while the raster is scanning somewhere else, otherwise there is a risk of disruption of the display. The position on screen of the upper left corner of each sprite, and the X and Y magnification, will be defined by five registers for each sprite: A2 A1 A0 0 0 0 X position LSB 0 0 1 X position MSB 0 1 0 Y position (scan line) LSB 0 1 1 Y position MSB 1 0 0 bits 3,2 = X magnification, bits 1,0 = Y magnification The position registers will be read/write, and will accept numbers in two's complement form. They should only be changed during retrace or when a sprite is off. Data written to these registers should be between +767 and -256 for X, and between +255 and -256 for Y, otherwise the sprites will appear in strange positions. With standard 6845 timing (64us scan lines, 200 visible lines), "on screen" positions at maximum sprite magnification are -64 to +639 in x and -63 to +199 in y. A sprite will not be displayed if either the vertical or the horizontal positions outside the on screen range. The magnification registers are cleared to zero at reset, and are write only. They are coded as: 0 0 Sprite not displayed 0 1 Magnification x1 1 0 Magnification x2 1 1 Magnification x4 The sprite control registers will exist on 8-byte boundaries from addresses 6000 to 607Fh for sprites 0 to 15 respectively. All sprite characteristics will be independent of the main screen mode, the unmagnified pixel size being as for screen mode 2 (640x200). Sprite colours will be defined by fifteen entries in the colour palette (see section 2.2 below). Thus sprites can be in different colours and resolutions from the rest of the screen. Sprites may overlay with each other or the border, and are prioritized so that the border has the highest priority, followed by sprites 0 to 15 in sequence, then the main screen data. Thus sprites always appear "in front of" the main screen and "behind" the border. 2.2 Colour palette The existing colour palette within the ASIC, which selects 17 of 27 possible colours, will be replaced by a new palette which selects 32 of 4096 colours. This will be accessed through two ports. The primary port will provide full access via 32 registers of 12 bits, i.e. 4 bits each for red, green and blue. For compatibility with existing models a secondary port will provide access to the first seventeen registers only (i.e. main screen colours and border), via the existing five bit interface. A block of logic will map the five bit colour written to the "palette memory" location onto the equivalent 12 bit colour, which is then written to the palette at the address selected by the "palette pointer register". The primary palette port is between addresses 6400 and 643Fh, each pair of bytes representing one entry in the palette. The most significant byte will contain the GREEN information in the lower nibble (D3-D0), and the other byte will contain RED (D7-D4) and BLUE (D3-D0). This ordering of colours has been selected to give the most consistent grey scale possible on a monochrome display (green is brighter than red, which is brighter than blue). However, because of the need to retain compatibility with the existing 27 level grey scale, the colours are summed with a 9:3:1 weighting rather than the 256:16:1 weighting which would be required to make the 12 bit word fully monotonic. The primary palette registers appear in RAM low byte first, so that they can be loaded via a single 16-bit LD instruction, e.g. LD (6400h),0F00h would set the main colour zero to bright green. The palette will be dual ported so that there are no restrictions on when it can be accessed. The primary port palette registers will be: 6400-641Fh main screen colours 0 to 15 6420-6421h border colour 6422-643Fh sprite colours 1 to 15 The secondary port registers will be: 00-0F main screen colours 0 to 15 10-1F border colour 2.3 Split Screen facility Three new memory mapped registers will be added within the ASIC, to provided a horizontally split screen facility. One at address 6801h will define the scan line after which the screen split occurs. A value of zero (as at power on reset) will turn this feature off. The other register pair at 6802h and 6803h define the start address in memory (similar to R12 and R13 respectively in the 6845, and therefore high byte first) which represents the location in memory from which to start displaying data for the lower screen. This will allow the lower part of the picture to come from a separate memory area, and be separately scrolled. However, note that soft scrolling (Section 2.5 below) will act on the whole screen. Note that care should be taken with programming this facility such that the screen split does not alter the function of address bits A1-A8 and the dynamic memory refresh is not upset. This can be accomplished by setting the start of the second screen to lie on a 16k boundary. Note that the value in register pair 6802h/6803h is the first displayed line, and not the start address of the 16k block. 2.4 Programmable raster interrupt A new 8 bit memory mapped register (PRI) will be added within the ASIC at address 6800h, which is cleared at power up. If zero, the normal raster interrupt mechanism will function as before. Otherwise, an interrupt will occur instead at the end of the scan line specified. In either case, this facility can provide a vectored interrupt (see section 2.7 below). The PRI can be reprogrammed as required to produce multiple interrupts per frame. 2.5 Soft scroll facility A memory mapped 8 bit soft scroll control register (SSCR) will be added within the ASIC at 6804h, to allow scrolling of the screen by pixels rather than just by characters as at present. It will be cleared at reset. This soft scrolling mechanism will affect the whole of the main screen, regardless of the split screen facility, but it will not affect sprites. The lower four bits (D3-D0) of the SSCR define a horizontal delay of between 0 and 15 bits i.e. high resolution (mode 2) pixels. This shifts the screen image to the right by the value programmed, "losing" pixels behind the right border and instead displaying random data on the left. It is left to the programmer to ensure that the delay value is always a multiple of the number of bits per pixel. The next three bits (D6-D4) will be added to the least significant three bits of the scan line address, thus determining which of the eight 2k blocks contains the data for the first scan line on the screen. The effect of this is to shift the display up by the number of scan lines programmed, "losing" what would otherwise be the first lines to be displayed, and instead appending extra lines to the bottom of the screen. The most significant bit (D7), when set, causes the border to extend over the first two bytes (16 high resolution pixels) of each scan line, masking out the bad data caused by the horizontal soft scroll. Software which intends to use horizontal soft scroll should have this bit always set, so that the screen width does not keep changing. Setting the SSCR to zero, as at reset, (i.e. no offsets, normal border), will of course effectively disable the soft scroll. 2.6 Automatic feeding of sound generator An automated process will be added to feed data to the sound generator from three instruction streams in main memory without CPU intervention. Three separate channels will each fetch one 16-bit instruction during horizontal retrace time. These instructions must be in usual Z-80 format, i.e. least significant byte first, and must be aligned to word boundaries (i.e. address of first byte must be even). Once the three instructions have been captured, they will then be executed sequentially. The maximum achievable update rate to the PSG is thus equal to the horizontal scan rate of 15.625 kHz per channel. The available commands are: 0RDDh LOAD R,D Load 8 bit data D to PSG register R (0<=R<=15) 1NNNh PAUSE N Pause for N prescaled ticks (0